From owner-freebsd-mips@FreeBSD.ORG Tue Oct 4 17:47:56 2011 Return-Path: Delivered-To: freebsd-mips@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id D8CA71065670; Tue, 4 Oct 2011 17:47:56 +0000 (UTC) (envelope-from c.jayachandran@gmail.com) Received: from mail-wy0-f182.google.com (mail-wy0-f182.google.com [74.125.82.182]) by mx1.freebsd.org (Postfix) with ESMTP id 18C958FC19; Tue, 4 Oct 2011 17:47:55 +0000 (UTC) Received: by wyj26 with SMTP id 26so1088628wyj.13 for ; Tue, 04 Oct 2011 10:47:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=mime-version:sender:in-reply-to:references:date :x-google-sender-auth:message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=s94I4xWp3RdnYhIWZPboLE6AgTzzzlS+kMjZwA2LJqo=; b=ANQZfRPeilPBBicuQbiGMIgkc/m4g6xKpxG3PXTtDQ/V4jcY9lwFHbsfA5Aj2rbv+f nyY5EZsjNNfnH+PSOPd8uGxp38SBrxXBEQSl6s6cUFWzOpr4i2ATz/z4pggkUxN8Ep+X lMGHtWOV4GTG/ejBXMe1m/hWXjqLm0l8etqvU= MIME-Version: 1.0 Received: by 10.216.14.201 with SMTP id d51mr1783461wed.56.1317750474859; Tue, 04 Oct 2011 10:47:54 -0700 (PDT) Sender: c.jayachandran@gmail.com Received: by 10.216.29.78 with HTTP; Tue, 4 Oct 2011 10:47:54 -0700 (PDT) In-Reply-To: References: Date: Tue, 4 Oct 2011 23:17:54 +0530 X-Google-Sender-Auth: bCVXIL3NSltuI3eXt7mp3cyeMFM Message-ID: From: "Jayachandran C." To: Andrew Duane Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Cc: Kostik Belousov , Alexander Motin , "freebsd-mips@freebsd.org" Subject: Re: svn commit: r225892 - head/sys/mips/mips X-BeenThere: freebsd-mips@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Porting FreeBSD to MIPS List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 04 Oct 2011 17:47:56 -0000 On Tue, Oct 4, 2011 at 9:34 PM, Andrew Duane wrote: > The MIPS manual volume 3 says there is a 3 cycle "typical" wait between a= n MTC0 that messes with Status[IE] and an interrupted instruction. That haz= ard doesn't seem to apply here, to any of the cases we have. > > I do have a question: in StartWaitSkip, the value of Status[IE] is being = toggled, not cleared. Is that correct? Do we always guarantee that it will = be set on entry here? Interrupts have to be enabled in cpu_idle(), there is an assert in the beginning of cpu_idle which checks this. > I had also made a comment about the "PTR_ADDU k1, 16 =A0 =A0# skip over w= ait" in MipsKernIntr; I think it would be safer (and clearer) to do "PTR_LA= =A0 =A0 =A0 =A0k1, EndWaitSkip" instead. Loading an immediate address takes more instructions (esp in 64 bit) adding 16 is just one instruction. I should really add an KASSERT somewhere to make sure that EndWaitSkip - StartWaitSkip is 16... JC.