From owner-svn-src-vendor@freebsd.org Sat Jun 3 15:20:39 2017 Return-Path: Delivered-To: svn-src-vendor@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 4C9EFBF387E; Sat, 3 Jun 2017 15:20:39 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id CCBE2732D8; Sat, 3 Jun 2017 15:20:38 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id v53FKbY5079616; Sat, 3 Jun 2017 15:20:37 GMT (envelope-from dim@FreeBSD.org) Received: (from dim@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id v53FKbEg079606; Sat, 3 Jun 2017 15:20:37 GMT (envelope-from dim@FreeBSD.org) Message-Id: <201706031520.v53FKbEg079606@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: dim set sender to dim@FreeBSD.org using -f From: Dimitry Andric Date: Sat, 3 Jun 2017 15:20:37 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-vendor@freebsd.org Subject: svn commit: r319523 - in vendor/llvm/dist: include/llvm include/llvm/ADT include/llvm/Analysis include/llvm/CodeGen include/llvm/CodeGen/PBQP include/llvm/DebugInfo/CodeView include/llvm/DebugInfo/... X-SVN-Group: vendor MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-vendor@freebsd.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: SVN commit messages for the vendor work area tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 03 Jun 2017 15:20:39 -0000 Author: dim Date: Sat Jun 3 15:20:36 2017 New Revision: 319523 URL: https://svnweb.freebsd.org/changeset/base/319523 Log: Vendor import of llvm trunk r304659: https://llvm.org/svn/llvm-project/llvm/trunk@304659 Added: vendor/llvm/dist/lib/Target/ARM/ARMScheduleA57.td vendor/llvm/dist/lib/Target/ARM/ARMScheduleA57WriteRes.td vendor/llvm/dist/test/CodeGen/AMDGPU/not-scalarize-volatile-load.ll vendor/llvm/dist/test/CodeGen/ARM/cortex-a57-misched-alu.ll vendor/llvm/dist/test/CodeGen/ARM/cortex-a57-misched-basic.ll vendor/llvm/dist/test/CodeGen/ARM/cortex-a57-misched-ldm-wrback.ll vendor/llvm/dist/test/CodeGen/ARM/cortex-a57-misched-ldm.ll vendor/llvm/dist/test/CodeGen/ARM/cortex-a57-misched-stm-wrback.ll vendor/llvm/dist/test/CodeGen/ARM/cortex-a57-misched-stm.ll vendor/llvm/dist/test/CodeGen/ARM/cortex-a57-misched-vfma.ll vendor/llvm/dist/test/CodeGen/ARM/cortex-a57-misched-vldm-wrback.ll vendor/llvm/dist/test/CodeGen/ARM/cortex-a57-misched-vldm.ll vendor/llvm/dist/test/CodeGen/ARM/cortex-a57-misched-vstm-wrback.ll vendor/llvm/dist/test/CodeGen/ARM/cortex-a57-misched-vstm.ll vendor/llvm/dist/test/CodeGen/Hexagon/newify-crash.ll vendor/llvm/dist/test/CodeGen/Mips/micromips-sizereduction/micromips-lbu16-lhu16-sb16-sh16.ll vendor/llvm/dist/test/CodeGen/PowerPC/scavenging.mir vendor/llvm/dist/test/CodeGen/SystemZ/RAbasic-invalid-LR-update.mir vendor/llvm/dist/test/CodeGen/X86/scavenger.mir vendor/llvm/dist/test/CodeGen/X86/vector-unsigned-cmp.ll vendor/llvm/dist/test/DebugInfo/MIR/AArch64/ vendor/llvm/dist/test/DebugInfo/MIR/AArch64/clobber-sp.mir vendor/llvm/dist/test/DebugInfo/MIR/AArch64/lit.local.cfg vendor/llvm/dist/test/Instrumentation/SanitizerCoverage/inline-8bit-counters.ll vendor/llvm/dist/test/MC/WebAssembly/external-data.ll vendor/llvm/dist/test/Transforms/CodeExtractor/cost.ll vendor/llvm/dist/test/Transforms/CodeExtractor/cost_meta.ll vendor/llvm/dist/test/Transforms/LowerExpectIntrinsic/phi_merge.ll vendor/llvm/dist/test/Transforms/LowerExpectIntrinsic/phi_or.ll vendor/llvm/dist/test/Transforms/LowerExpectIntrinsic/phi_tern.ll vendor/llvm/dist/test/Transforms/LowerTypeTests/Inputs/use-typeid1-dead.yaml vendor/llvm/dist/test/Transforms/LowerTypeTests/export-dead.ll vendor/llvm/dist/test/Transforms/Util/PredicateInfo/condprop2.ll vendor/llvm/dist/test/Transforms/Util/PredicateInfo/testandor2.ll vendor/llvm/dist/unittests/Analysis/OrderedBasicBlockTest.cpp (contents, props changed) Modified: vendor/llvm/dist/include/llvm/ADT/SmallVector.h vendor/llvm/dist/include/llvm/Analysis/OrderedBasicBlock.h vendor/llvm/dist/include/llvm/Analysis/RegionPass.h vendor/llvm/dist/include/llvm/Analysis/ScalarEvolution.h vendor/llvm/dist/include/llvm/CodeGen/MachineRegionInfo.h vendor/llvm/dist/include/llvm/CodeGen/MachineRegisterInfo.h vendor/llvm/dist/include/llvm/CodeGen/MachineScheduler.h vendor/llvm/dist/include/llvm/CodeGen/PBQP/CostAllocator.h vendor/llvm/dist/include/llvm/CodeGen/PBQP/Graph.h vendor/llvm/dist/include/llvm/CodeGen/PBQP/Math.h vendor/llvm/dist/include/llvm/CodeGen/PBQP/ReductionRules.h vendor/llvm/dist/include/llvm/CodeGen/PBQP/Solution.h vendor/llvm/dist/include/llvm/CodeGen/PBQPRAConstraint.h vendor/llvm/dist/include/llvm/CodeGen/Passes.h vendor/llvm/dist/include/llvm/CodeGen/RegAllocPBQP.h vendor/llvm/dist/include/llvm/CodeGen/RegisterScavenging.h vendor/llvm/dist/include/llvm/CodeGen/ScheduleDAGInstrs.h vendor/llvm/dist/include/llvm/CodeGen/SelectionDAG.h vendor/llvm/dist/include/llvm/CodeGen/SelectionDAGNodes.h vendor/llvm/dist/include/llvm/CodeGen/SlotIndexes.h vendor/llvm/dist/include/llvm/CodeGen/StackMaps.h vendor/llvm/dist/include/llvm/CodeGen/TargetSchedule.h vendor/llvm/dist/include/llvm/CodeGen/WinEHFuncInfo.h vendor/llvm/dist/include/llvm/DebugInfo/CodeView/CodeView.h vendor/llvm/dist/include/llvm/DebugInfo/CodeView/CodeViewRecordIO.h vendor/llvm/dist/include/llvm/DebugInfo/CodeView/DebugChecksumsSubsection.h vendor/llvm/dist/include/llvm/DebugInfo/CodeView/DebugInlineeLinesSubsection.h vendor/llvm/dist/include/llvm/DebugInfo/CodeView/DebugSubsectionRecord.h vendor/llvm/dist/include/llvm/DebugInfo/CodeView/SymbolDeserializer.h vendor/llvm/dist/include/llvm/DebugInfo/CodeView/SymbolDumper.h vendor/llvm/dist/include/llvm/DebugInfo/CodeView/SymbolRecordMapping.h vendor/llvm/dist/include/llvm/DebugInfo/CodeView/SymbolSerializer.h vendor/llvm/dist/include/llvm/DebugInfo/MSF/MappedBlockStream.h vendor/llvm/dist/include/llvm/DebugInfo/PDB/Native/DbiModuleDescriptorBuilder.h vendor/llvm/dist/include/llvm/DebugInfo/PDB/Native/ModuleDebugStream.h vendor/llvm/dist/include/llvm/DebugInfo/PDB/Native/PDBStringTable.h vendor/llvm/dist/include/llvm/DebugInfo/PDB/Native/TpiStream.h vendor/llvm/dist/include/llvm/IR/DIBuilder.h vendor/llvm/dist/include/llvm/IR/DebugLoc.h vendor/llvm/dist/include/llvm/IR/ModuleSummaryIndex.h vendor/llvm/dist/include/llvm/IR/ModuleSummaryIndexYAML.h vendor/llvm/dist/include/llvm/IR/Statepoint.h vendor/llvm/dist/include/llvm/InitializePasses.h vendor/llvm/dist/include/llvm/LTO/Config.h vendor/llvm/dist/include/llvm/ObjectYAML/CodeViewYAMLDebugSections.h vendor/llvm/dist/include/llvm/ObjectYAML/CodeViewYAMLSymbols.h vendor/llvm/dist/include/llvm/TableGen/Record.h vendor/llvm/dist/include/llvm/Transforms/IPO/FunctionImport.h vendor/llvm/dist/include/llvm/Transforms/Instrumentation.h vendor/llvm/dist/include/llvm/Transforms/Utils/Cloning.h vendor/llvm/dist/lib/Analysis/ConstantFolding.cpp vendor/llvm/dist/lib/Analysis/IndirectCallPromotionAnalysis.cpp vendor/llvm/dist/lib/Analysis/InlineCost.cpp vendor/llvm/dist/lib/Analysis/LazyValueInfo.cpp vendor/llvm/dist/lib/Analysis/ModuleSummaryAnalysis.cpp vendor/llvm/dist/lib/Analysis/OrderedBasicBlock.cpp vendor/llvm/dist/lib/Analysis/RegionPass.cpp vendor/llvm/dist/lib/Bitcode/Reader/BitcodeReader.cpp vendor/llvm/dist/lib/Bitcode/Writer/BitcodeWriter.cpp vendor/llvm/dist/lib/CodeGen/AsmPrinter/DbgValueHistoryCalculator.cpp vendor/llvm/dist/lib/CodeGen/CodeGen.cpp vendor/llvm/dist/lib/CodeGen/GlobalMerge.cpp vendor/llvm/dist/lib/CodeGen/LivePhysRegs.cpp vendor/llvm/dist/lib/CodeGen/LiveRegUnits.cpp vendor/llvm/dist/lib/CodeGen/MachineRegionInfo.cpp vendor/llvm/dist/lib/CodeGen/MachineVerifier.cpp vendor/llvm/dist/lib/CodeGen/PrologEpilogInserter.cpp vendor/llvm/dist/lib/CodeGen/RegAllocBasic.cpp vendor/llvm/dist/lib/CodeGen/RegAllocPBQP.cpp vendor/llvm/dist/lib/CodeGen/RegisterScavenging.cpp vendor/llvm/dist/lib/CodeGen/ScheduleDAGInstrs.cpp vendor/llvm/dist/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp vendor/llvm/dist/lib/CodeGen/SelectionDAG/SelectionDAG.cpp vendor/llvm/dist/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp vendor/llvm/dist/lib/CodeGen/SelectionDAG/StatepointLowering.cpp vendor/llvm/dist/lib/CodeGen/SelectionDAG/TargetLowering.cpp vendor/llvm/dist/lib/CodeGen/TargetLoweringBase.cpp vendor/llvm/dist/lib/DebugInfo/CodeView/CodeViewRecordIO.cpp vendor/llvm/dist/lib/DebugInfo/CodeView/DebugStringTableSubsection.cpp vendor/llvm/dist/lib/DebugInfo/CodeView/DebugSubsectionRecord.cpp vendor/llvm/dist/lib/DebugInfo/CodeView/SymbolDumper.cpp vendor/llvm/dist/lib/DebugInfo/CodeView/SymbolRecordMapping.cpp vendor/llvm/dist/lib/DebugInfo/CodeView/SymbolSerializer.cpp vendor/llvm/dist/lib/DebugInfo/MSF/MappedBlockStream.cpp vendor/llvm/dist/lib/DebugInfo/PDB/Native/DbiModuleDescriptorBuilder.cpp vendor/llvm/dist/lib/DebugInfo/PDB/Native/DbiStream.cpp vendor/llvm/dist/lib/DebugInfo/PDB/Native/DbiStreamBuilder.cpp vendor/llvm/dist/lib/DebugInfo/PDB/Native/InfoStreamBuilder.cpp vendor/llvm/dist/lib/DebugInfo/PDB/Native/ModuleDebugStream.cpp vendor/llvm/dist/lib/DebugInfo/PDB/Native/PDBFile.cpp vendor/llvm/dist/lib/DebugInfo/PDB/Native/PDBFileBuilder.cpp vendor/llvm/dist/lib/DebugInfo/PDB/Native/PDBStringTable.cpp vendor/llvm/dist/lib/DebugInfo/PDB/Native/TpiStream.cpp vendor/llvm/dist/lib/DebugInfo/PDB/Native/TpiStreamBuilder.cpp vendor/llvm/dist/lib/IR/DIBuilder.cpp vendor/llvm/dist/lib/IR/DebugLoc.cpp vendor/llvm/dist/lib/IR/OptBisect.cpp vendor/llvm/dist/lib/LTO/LTO.cpp vendor/llvm/dist/lib/LTO/LTOBackend.cpp vendor/llvm/dist/lib/LTO/ThinLTOCodeGenerator.cpp vendor/llvm/dist/lib/MC/WasmObjectWriter.cpp vendor/llvm/dist/lib/ObjectYAML/CodeViewYAMLDebugSections.cpp vendor/llvm/dist/lib/ObjectYAML/CodeViewYAMLSymbols.cpp vendor/llvm/dist/lib/Passes/PassBuilder.cpp vendor/llvm/dist/lib/Support/Triple.cpp vendor/llvm/dist/lib/Target/AArch64/AArch64PBQPRegAlloc.h vendor/llvm/dist/lib/Target/AArch64/AArch64SchedFalkorDetails.td vendor/llvm/dist/lib/Target/AMDGPU/AMDGPU.h vendor/llvm/dist/lib/Target/AMDGPU/AMDGPU.td vendor/llvm/dist/lib/Target/AMDGPU/AMDGPUAlwaysInlinePass.cpp vendor/llvm/dist/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp vendor/llvm/dist/lib/Target/AMDGPU/AMDGPUSubtarget.cpp vendor/llvm/dist/lib/Target/AMDGPU/AMDGPUSubtarget.h vendor/llvm/dist/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp vendor/llvm/dist/lib/Target/AMDGPU/SIFoldOperands.cpp vendor/llvm/dist/lib/Target/AMDGPU/SIISelLowering.cpp vendor/llvm/dist/lib/Target/AMDGPU/SIInsertWaitcnts.cpp vendor/llvm/dist/lib/Target/AMDGPU/SIInsertWaits.cpp vendor/llvm/dist/lib/Target/AMDGPU/SMInstructions.td vendor/llvm/dist/lib/Target/AMDGPU/VOP3Instructions.td vendor/llvm/dist/lib/Target/ARM/ARM.td vendor/llvm/dist/lib/Target/ARM/ARMBaseInstrInfo.cpp vendor/llvm/dist/lib/Target/ARM/ARMBaseInstrInfo.h vendor/llvm/dist/lib/Target/ARM/ARMCallLowering.cpp vendor/llvm/dist/lib/Target/ARM/ARMSchedule.td vendor/llvm/dist/lib/Target/ARM/ARMSubtarget.h vendor/llvm/dist/lib/Target/Hexagon/HexagonInstrInfo.cpp vendor/llvm/dist/lib/Target/Mips/MicroMipsSizeReduction.cpp vendor/llvm/dist/lib/Target/WebAssembly/known_gcc_test_failures.txt vendor/llvm/dist/lib/Target/X86/X86ISelLowering.cpp vendor/llvm/dist/lib/Transforms/Coroutines/CoroSplit.cpp vendor/llvm/dist/lib/Transforms/Coroutines/Coroutines.cpp vendor/llvm/dist/lib/Transforms/IPO/FunctionAttrs.cpp vendor/llvm/dist/lib/Transforms/IPO/FunctionImport.cpp vendor/llvm/dist/lib/Transforms/IPO/LowerTypeTests.cpp vendor/llvm/dist/lib/Transforms/IPO/PartialInlining.cpp vendor/llvm/dist/lib/Transforms/IPO/PassManagerBuilder.cpp vendor/llvm/dist/lib/Transforms/InstCombine/InstCombineCompares.cpp vendor/llvm/dist/lib/Transforms/Instrumentation/MemorySanitizer.cpp vendor/llvm/dist/lib/Transforms/Instrumentation/SanitizerCoverage.cpp vendor/llvm/dist/lib/Transforms/Scalar/IndVarSimplify.cpp vendor/llvm/dist/lib/Transforms/Scalar/LowerExpectIntrinsic.cpp vendor/llvm/dist/lib/Transforms/Scalar/RewriteStatepointsForGC.cpp vendor/llvm/dist/lib/Transforms/Scalar/SROA.cpp vendor/llvm/dist/lib/Transforms/Utils/CloneFunction.cpp vendor/llvm/dist/lib/Transforms/Vectorize/LoopVectorize.cpp vendor/llvm/dist/lib/Transforms/Vectorize/SLPVectorizer.cpp vendor/llvm/dist/runtimes/CMakeLists.txt vendor/llvm/dist/test/CodeGen/AMDGPU/GlobalISel/legalize-constant.mir vendor/llvm/dist/test/CodeGen/AMDGPU/basic-branch.ll vendor/llvm/dist/test/CodeGen/AMDGPU/branch-condition-and.ll vendor/llvm/dist/test/CodeGen/AMDGPU/branch-relaxation.ll vendor/llvm/dist/test/CodeGen/AMDGPU/commute-compares.ll vendor/llvm/dist/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll vendor/llvm/dist/test/CodeGen/AMDGPU/indirect-addressing-si.ll vendor/llvm/dist/test/CodeGen/AMDGPU/infinite-loop.ll vendor/llvm/dist/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll vendor/llvm/dist/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.store.format.ll vendor/llvm/dist/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.store.ll vendor/llvm/dist/test/CodeGen/AMDGPU/llvm.amdgcn.ds.swizzle.ll vendor/llvm/dist/test/CodeGen/AMDGPU/llvm.amdgcn.image.ll vendor/llvm/dist/test/CodeGen/AMDGPU/llvm.amdgcn.kernarg.segment.ptr.ll vendor/llvm/dist/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll vendor/llvm/dist/test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.inv.ll vendor/llvm/dist/test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.inv.vol.ll vendor/llvm/dist/test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.wb.ll vendor/llvm/dist/test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.wb.vol.ll vendor/llvm/dist/test/CodeGen/AMDGPU/llvm.amdgcn.s.waitcnt.ll vendor/llvm/dist/test/CodeGen/AMDGPU/multi-divergent-exit-region.ll vendor/llvm/dist/test/CodeGen/AMDGPU/ret_jump.ll vendor/llvm/dist/test/CodeGen/AMDGPU/si-lower-control-flow-unreachable-block.ll vendor/llvm/dist/test/CodeGen/AMDGPU/smrd-vccz-bug.ll vendor/llvm/dist/test/CodeGen/AMDGPU/spill-m0.ll vendor/llvm/dist/test/CodeGen/AMDGPU/sub.i16.ll vendor/llvm/dist/test/CodeGen/AMDGPU/valu-i1.ll vendor/llvm/dist/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll vendor/llvm/dist/test/CodeGen/ARM/GlobalISel/arm-unsupported.ll vendor/llvm/dist/test/CodeGen/ARM/global-merge-external.ll vendor/llvm/dist/test/CodeGen/MIR/Generic/runPass.mir vendor/llvm/dist/test/CodeGen/X86/and-sink.ll vendor/llvm/dist/test/CodeGen/X86/avx512-cvt.ll vendor/llvm/dist/test/CodeGen/X86/broadcast-elm-cross-splat-vec.ll vendor/llvm/dist/test/CodeGen/X86/clear_upper_vector_element_bits.ll vendor/llvm/dist/test/CodeGen/X86/select.ll vendor/llvm/dist/test/CodeGen/X86/shrink-compare.ll vendor/llvm/dist/test/CodeGen/X86/sse3.ll vendor/llvm/dist/test/CodeGen/X86/stack-folding-fp-avx1.ll vendor/llvm/dist/test/CodeGen/X86/statepoint-allocas.ll vendor/llvm/dist/test/CodeGen/X86/statepoint-call-lowering.ll vendor/llvm/dist/test/CodeGen/X86/statepoint-far-call.ll vendor/llvm/dist/test/CodeGen/X86/statepoint-forward.ll vendor/llvm/dist/test/CodeGen/X86/statepoint-gctransition-call-lowering.ll vendor/llvm/dist/test/CodeGen/X86/statepoint-invoke.ll vendor/llvm/dist/test/CodeGen/X86/statepoint-live-in.ll vendor/llvm/dist/test/CodeGen/X86/statepoint-stack-usage.ll vendor/llvm/dist/test/CodeGen/X86/statepoint-stackmap-format.ll vendor/llvm/dist/test/CodeGen/X86/statepoint-uniqueing.ll vendor/llvm/dist/test/CodeGen/X86/statepoint-vector-bad-spill.ll vendor/llvm/dist/test/CodeGen/X86/statepoint-vector.ll vendor/llvm/dist/test/CodeGen/X86/wide-fma-contraction.ll vendor/llvm/dist/test/CodeGen/X86/xor-icmp.ll vendor/llvm/dist/test/DebugInfo/PDB/Inputs/simple-line-info.yaml vendor/llvm/dist/test/DebugInfo/PDB/pdbdump-write.test vendor/llvm/dist/test/DebugInfo/PDB/pdbdump-yaml-lineinfo.test vendor/llvm/dist/test/ThinLTO/X86/deadstrip.ll vendor/llvm/dist/test/ThinLTO/X86/newpm-basic.ll vendor/llvm/dist/test/Transforms/Coroutines/coro-split-02.ll vendor/llvm/dist/test/Transforms/Inline/AArch64/switch.ll vendor/llvm/dist/test/Transforms/InstCombine/not.ll vendor/llvm/dist/test/Transforms/InstSimplify/compare.ll vendor/llvm/dist/test/Transforms/LowerTypeTests/Inputs/import-unsat.yaml vendor/llvm/dist/test/Transforms/LowerTypeTests/Inputs/use-typeid1-typeid2.yaml vendor/llvm/dist/test/Transforms/LowerTypeTests/export-nothing.ll vendor/llvm/dist/test/Transforms/LowerTypeTests/import-unsat.ll vendor/llvm/dist/test/Transforms/SROA/address-spaces.ll vendor/llvm/dist/test/Transforms/Util/PredicateInfo/condprop.ll vendor/llvm/dist/test/Transforms/Util/PredicateInfo/testandor.ll vendor/llvm/dist/test/Transforms/WholeProgramDevirt/Inputs/export.yaml vendor/llvm/dist/test/Transforms/WholeProgramDevirt/Inputs/import-indir.yaml vendor/llvm/dist/test/Transforms/WholeProgramDevirt/export-nothing.ll vendor/llvm/dist/test/Transforms/WholeProgramDevirt/export-single-impl.ll vendor/llvm/dist/test/Transforms/WholeProgramDevirt/export-uniform-ret-val.ll vendor/llvm/dist/test/Transforms/WholeProgramDevirt/export-unique-ret-val.ll vendor/llvm/dist/test/Transforms/WholeProgramDevirt/export-unsuccessful-checked.ll vendor/llvm/dist/test/Transforms/WholeProgramDevirt/import-indir.ll vendor/llvm/dist/test/tools/llvm-lto2/X86/pipeline.ll vendor/llvm/dist/tools/llc/llc.cpp vendor/llvm/dist/tools/llvm-config/llvm-config.cpp vendor/llvm/dist/tools/llvm-lto2/llvm-lto2.cpp vendor/llvm/dist/tools/llvm-pdbdump/LLVMOutputStyle.cpp vendor/llvm/dist/tools/llvm-pdbdump/PdbYaml.cpp vendor/llvm/dist/tools/llvm-pdbdump/PdbYaml.h vendor/llvm/dist/tools/llvm-pdbdump/YAMLOutputStyle.cpp vendor/llvm/dist/tools/llvm-pdbdump/YAMLOutputStyle.h vendor/llvm/dist/tools/llvm-pdbdump/fuzzer/llvm-pdbdump-fuzzer.cpp vendor/llvm/dist/tools/llvm-pdbdump/llvm-pdbdump.cpp vendor/llvm/dist/tools/llvm-readobj/COFFDumper.cpp vendor/llvm/dist/unittests/ADT/SmallVectorTest.cpp vendor/llvm/dist/unittests/Analysis/CMakeLists.txt vendor/llvm/dist/unittests/DebugInfo/PDB/MappedBlockStreamTest.cpp vendor/llvm/dist/unittests/Transforms/Utils/Cloning.cpp vendor/llvm/dist/utils/TableGen/X86FoldTablesEmitter.cpp vendor/llvm/dist/utils/lit/lit/util.py Modified: vendor/llvm/dist/include/llvm/ADT/SmallVector.h ============================================================================== --- vendor/llvm/dist/include/llvm/ADT/SmallVector.h Sat Jun 3 14:45:46 2017 (r319522) +++ vendor/llvm/dist/include/llvm/ADT/SmallVector.h Sat Jun 3 15:20:36 2017 (r319523) @@ -415,12 +415,20 @@ class SmallVectorImpl : public SmallVectorTemplateBase append(IL.begin(), IL.end()); } + // FIXME: Consider assigning over existing elements, rather than clearing & + // re-initializing them - for all assign(...) variants. + void assign(size_type NumElts, const T &Elt) { clear(); if (this->capacity() < NumElts) this->grow(NumElts); this->setEnd(this->begin()+NumElts); std::uninitialized_fill(this->begin(), this->end(), Elt); + } + + template void assign(in_iter in_start, in_iter in_end) { + clear(); + append(in_start, in_end); } void assign(std::initializer_list IL) { Modified: vendor/llvm/dist/include/llvm/Analysis/OrderedBasicBlock.h ============================================================================== --- vendor/llvm/dist/include/llvm/Analysis/OrderedBasicBlock.h Sat Jun 3 14:45:46 2017 (r319522) +++ vendor/llvm/dist/include/llvm/Analysis/OrderedBasicBlock.h Sat Jun 3 15:20:36 2017 (r319523) @@ -58,6 +58,7 @@ class OrderedBasicBlock { (public) /// comes before \p B in \p BB. This is a simplification that considers /// cached instruction positions and ignores other basic blocks, being /// only relevant to compare relative instructions positions inside \p BB. + /// Returns false for A == B. bool dominates(const Instruction *A, const Instruction *B); }; Modified: vendor/llvm/dist/include/llvm/Analysis/RegionPass.h ============================================================================== --- vendor/llvm/dist/include/llvm/Analysis/RegionPass.h Sat Jun 3 14:45:46 2017 (r319522) +++ vendor/llvm/dist/include/llvm/Analysis/RegionPass.h Sat Jun 3 15:20:36 2017 (r319523) @@ -78,6 +78,11 @@ class RegionPass : public Pass { (public) return PMT_RegionPassManager; } //@} + +protected: + /// Optional passes call this function to check whether the pass should be + /// skipped. This is the case when optimization bisect is over the limit. + bool skipRegion(Region &R) const; }; /// @brief The pass manager to schedule RegionPasses. Modified: vendor/llvm/dist/include/llvm/Analysis/ScalarEvolution.h ============================================================================== --- vendor/llvm/dist/include/llvm/Analysis/ScalarEvolution.h Sat Jun 3 14:45:46 2017 (r319522) +++ vendor/llvm/dist/include/llvm/Analysis/ScalarEvolution.h Sat Jun 3 15:20:36 2017 (r319523) @@ -636,7 +636,7 @@ class ScalarEvolution { (private) /// @} public: - BackedgeTakenInfo() : MaxAndComplete(nullptr, 0) {} + BackedgeTakenInfo() : MaxAndComplete(nullptr, 0), MaxOrZero(false) {} BackedgeTakenInfo(BackedgeTakenInfo &&) = default; BackedgeTakenInfo &operator=(BackedgeTakenInfo &&) = default; Modified: vendor/llvm/dist/include/llvm/CodeGen/MachineRegionInfo.h ============================================================================== --- vendor/llvm/dist/include/llvm/CodeGen/MachineRegionInfo.h Sat Jun 3 14:45:46 2017 (r319522) +++ vendor/llvm/dist/include/llvm/CodeGen/MachineRegionInfo.h Sat Jun 3 15:20:36 2017 (r319523) @@ -10,83 +10,77 @@ #ifndef LLVM_CODEGEN_MACHINEREGIONINFO_H #define LLVM_CODEGEN_MACHINEREGIONINFO_H +#include "llvm/ADT/DepthFirstIterator.h" #include "llvm/Analysis/RegionInfo.h" #include "llvm/Analysis/RegionIterator.h" +#include "llvm/CodeGen/MachineBasicBlock.h" #include "llvm/CodeGen/MachineDominanceFrontier.h" #include "llvm/CodeGen/MachineDominators.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineLoopInfo.h" +#include - namespace llvm { -class MachineDominatorTree; struct MachinePostDominatorTree; class MachineRegion; class MachineRegionNode; class MachineRegionInfo; -template<> -struct RegionTraits { - typedef MachineFunction FuncT; - typedef MachineBasicBlock BlockT; - typedef MachineRegion RegionT; - typedef MachineRegionNode RegionNodeT; - typedef MachineRegionInfo RegionInfoT; - typedef MachineDominatorTree DomTreeT; - typedef MachineDomTreeNode DomTreeNodeT; - typedef MachinePostDominatorTree PostDomTreeT; - typedef MachineDominanceFrontier DomFrontierT; - typedef MachineInstr InstT; - typedef MachineLoop LoopT; - typedef MachineLoopInfo LoopInfoT; +template <> struct RegionTraits { + using FuncT = MachineFunction; + using BlockT = MachineBasicBlock; + using RegionT = MachineRegion; + using RegionNodeT = MachineRegionNode; + using RegionInfoT = MachineRegionInfo; + using DomTreeT = MachineDominatorTree; + using DomTreeNodeT = MachineDomTreeNode; + using PostDomTreeT = MachinePostDominatorTree; + using DomFrontierT = MachineDominanceFrontier; + using InstT = MachineInstr; + using LoopT = MachineLoop; + using LoopInfoT = MachineLoopInfo; static unsigned getNumSuccessors(MachineBasicBlock *BB) { return BB->succ_size(); } }; - class MachineRegionNode : public RegionNodeBase> { public: - inline MachineRegionNode(MachineRegion *Parent, - MachineBasicBlock *Entry, + inline MachineRegionNode(MachineRegion *Parent, MachineBasicBlock *Entry, bool isSubRegion = false) - : RegionNodeBase>(Parent, Entry, isSubRegion) { + : RegionNodeBase>(Parent, Entry, + isSubRegion) {} - } - bool operator==(const MachineRegion &RN) const { - return this == reinterpret_cast(&RN); + return this == reinterpret_cast(&RN); } }; class MachineRegion : public RegionBase> { public: MachineRegion(MachineBasicBlock *Entry, MachineBasicBlock *Exit, - MachineRegionInfo* RI, - MachineDominatorTree *DT, MachineRegion *Parent = nullptr); + MachineRegionInfo *RI, MachineDominatorTree *DT, + MachineRegion *Parent = nullptr); ~MachineRegion(); bool operator==(const MachineRegionNode &RN) const { - return &RN == reinterpret_cast(this); + return &RN == reinterpret_cast(this); } }; class MachineRegionInfo : public RegionInfoBase> { public: explicit MachineRegionInfo(); - ~MachineRegionInfo() override; // updateStatistics - Update statistic about created regions. void updateStatistics(MachineRegion *R) final; - void recalculate(MachineFunction &F, - MachineDominatorTree *DT, - MachinePostDominatorTree *PDT, - MachineDominanceFrontier *DF); + void recalculate(MachineFunction &F, MachineDominatorTree *DT, + MachinePostDominatorTree *PDT, MachineDominanceFrontier *DF); }; class MachineRegionInfoPass : public MachineFunctionPass { @@ -94,17 +88,13 @@ class MachineRegionInfoPass : public MachineFunctionPa public: static char ID; - explicit MachineRegionInfoPass(); + explicit MachineRegionInfoPass(); ~MachineRegionInfoPass() override; - MachineRegionInfo &getRegionInfo() { - return RI; - } + MachineRegionInfo &getRegionInfo() { return RI; } - const MachineRegionInfo &getRegionInfo() const { - return RI; - } + const MachineRegionInfo &getRegionInfo() const { return RI; } /// @name MachineFunctionPass interface //@{ @@ -117,66 +107,76 @@ class MachineRegionInfoPass : public MachineFunctionPa //@} }; - template <> template <> -inline MachineBasicBlock* RegionNodeBase>::getNodeAs() const { +inline MachineBasicBlock * +RegionNodeBase>::getNodeAs() + const { assert(!isSubRegion() && "This is not a MachineBasicBlock RegionNode!"); return getEntry(); } -template<> -template<> -inline MachineRegion* RegionNodeBase>::getNodeAs() const { +template <> +template <> +inline MachineRegion * +RegionNodeBase>::getNodeAs() + const { assert(isSubRegion() && "This is not a subregion RegionNode!"); - auto Unconst = const_cast>*>(this); - return reinterpret_cast(Unconst); + auto Unconst = + const_cast> *>(this); + return reinterpret_cast(Unconst); } - RegionNodeGraphTraits(MachineRegionNode, MachineBasicBlock, MachineRegion); -RegionNodeGraphTraits(const MachineRegionNode, MachineBasicBlock, MachineRegion); +RegionNodeGraphTraits(const MachineRegionNode, MachineBasicBlock, + MachineRegion); RegionGraphTraits(MachineRegion, MachineRegionNode); RegionGraphTraits(const MachineRegion, const MachineRegionNode); -template <> struct GraphTraits - : public GraphTraits > { - typedef df_iterator, false, - GraphTraits>> - nodes_iterator; +template <> +struct GraphTraits + : public GraphTraits> { + using nodes_iterator = df_iterator, + false, GraphTraits>>; static NodeRef getEntryNode(MachineRegionInfo *RI) { - return GraphTraits >::getEntryNode(RI->getTopLevelRegion()); + return GraphTraits>::getEntryNode( + RI->getTopLevelRegion()); } - static nodes_iterator nodes_begin(MachineRegionInfo* RI) { + + static nodes_iterator nodes_begin(MachineRegionInfo *RI) { return nodes_iterator::begin(getEntryNode(RI)); } + static nodes_iterator nodes_end(MachineRegionInfo *RI) { return nodes_iterator::end(getEntryNode(RI)); } }; -template <> struct GraphTraits - : public GraphTraits { - typedef df_iterator, false, - GraphTraits>> - nodes_iterator; +template <> +struct GraphTraits + : public GraphTraits { + using nodes_iterator = df_iterator, + false, GraphTraits>>; static NodeRef getEntryNode(MachineRegionInfoPass *RI) { - return GraphTraits::getEntryNode(&RI->getRegionInfo()); + return GraphTraits::getEntryNode(&RI->getRegionInfo()); } - static nodes_iterator nodes_begin(MachineRegionInfoPass* RI) { - return GraphTraits::nodes_begin(&RI->getRegionInfo()); + + static nodes_iterator nodes_begin(MachineRegionInfoPass *RI) { + return GraphTraits::nodes_begin(&RI->getRegionInfo()); } + static nodes_iterator nodes_end(MachineRegionInfoPass *RI) { - return GraphTraits::nodes_end(&RI->getRegionInfo()); + return GraphTraits::nodes_end(&RI->getRegionInfo()); } }; extern template class RegionBase>; extern template class RegionNodeBase>; extern template class RegionInfoBase>; -} -#endif +} // end namespace llvm + +#endif // LLVM_CODEGEN_MACHINEREGIONINFO_H Modified: vendor/llvm/dist/include/llvm/CodeGen/MachineRegisterInfo.h ============================================================================== --- vendor/llvm/dist/include/llvm/CodeGen/MachineRegisterInfo.h Sat Jun 3 14:45:46 2017 (r319522) +++ vendor/llvm/dist/include/llvm/CodeGen/MachineRegisterInfo.h Sat Jun 3 15:20:36 2017 (r319523) @@ -14,11 +14,13 @@ #ifndef LLVM_CODEGEN_MACHINEREGISTERINFO_H #define LLVM_CODEGEN_MACHINEREGISTERINFO_H +#include "llvm/ADT/ArrayRef.h" #include "llvm/ADT/BitVector.h" #include "llvm/ADT/DenseMap.h" #include "llvm/ADT/IndexedMap.h" #include "llvm/ADT/iterator_range.h" #include "llvm/ADT/PointerUnion.h" +#include "llvm/ADT/SmallVector.h" #include "llvm/CodeGen/GlobalISel/RegisterBank.h" #include "llvm/CodeGen/LowLevelType.h" #include "llvm/CodeGen/MachineBasicBlock.h" @@ -41,8 +43,8 @@ namespace llvm { class PSetIterator; /// Convenient type to represent either a register class or a register bank. -typedef PointerUnion - RegClassOrRegBank; +using RegClassOrRegBank = + PointerUnion; /// MachineRegisterInfo - Keep track of information for virtual and physical /// registers, including vreg register classes, use/def chains for registers, @@ -125,7 +127,7 @@ class MachineRegisterInfo { (private) /// started. BitVector ReservedRegs; - typedef DenseMap VRegToTypeMap; + using VRegToTypeMap = DenseMap; /// Map generic virtual registers to their actual size. mutable std::unique_ptr VRegToType; @@ -266,8 +268,8 @@ class MachineRegisterInfo { (private) /// reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified /// register. - typedef defusechain_iterator - reg_iterator; + using reg_iterator = + defusechain_iterator; reg_iterator reg_begin(unsigned RegNo) const { return reg_iterator(getRegUseDefListHead(RegNo)); } @@ -279,8 +281,8 @@ class MachineRegisterInfo { (private) /// reg_instr_iterator/reg_instr_begin/reg_instr_end - Walk all defs and uses /// of the specified register, stepping by MachineInstr. - typedef defusechain_instr_iterator - reg_instr_iterator; + using reg_instr_iterator = + defusechain_instr_iterator; reg_instr_iterator reg_instr_begin(unsigned RegNo) const { return reg_instr_iterator(getRegUseDefListHead(RegNo)); } @@ -295,8 +297,8 @@ class MachineRegisterInfo { (private) /// reg_bundle_iterator/reg_bundle_begin/reg_bundle_end - Walk all defs and uses /// of the specified register, stepping by bundle. - typedef defusechain_instr_iterator - reg_bundle_iterator; + using reg_bundle_iterator = + defusechain_instr_iterator; reg_bundle_iterator reg_bundle_begin(unsigned RegNo) const { return reg_bundle_iterator(getRegUseDefListHead(RegNo)); } @@ -314,8 +316,8 @@ class MachineRegisterInfo { (private) /// reg_nodbg_iterator/reg_nodbg_begin/reg_nodbg_end - Walk all defs and uses /// of the specified register, skipping those marked as Debug. - typedef defusechain_iterator - reg_nodbg_iterator; + using reg_nodbg_iterator = + defusechain_iterator; reg_nodbg_iterator reg_nodbg_begin(unsigned RegNo) const { return reg_nodbg_iterator(getRegUseDefListHead(RegNo)); } @@ -331,8 +333,8 @@ class MachineRegisterInfo { (private) /// reg_instr_nodbg_iterator/reg_instr_nodbg_begin/reg_instr_nodbg_end - Walk /// all defs and uses of the specified register, stepping by MachineInstr, /// skipping those marked as Debug. - typedef defusechain_instr_iterator - reg_instr_nodbg_iterator; + using reg_instr_nodbg_iterator = + defusechain_instr_iterator; reg_instr_nodbg_iterator reg_instr_nodbg_begin(unsigned RegNo) const { return reg_instr_nodbg_iterator(getRegUseDefListHead(RegNo)); } @@ -348,8 +350,8 @@ class MachineRegisterInfo { (private) /// reg_bundle_nodbg_iterator/reg_bundle_nodbg_begin/reg_bundle_nodbg_end - Walk /// all defs and uses of the specified register, stepping by bundle, /// skipping those marked as Debug. - typedef defusechain_instr_iterator - reg_bundle_nodbg_iterator; + using reg_bundle_nodbg_iterator = + defusechain_instr_iterator; reg_bundle_nodbg_iterator reg_bundle_nodbg_begin(unsigned RegNo) const { return reg_bundle_nodbg_iterator(getRegUseDefListHead(RegNo)); } @@ -369,8 +371,8 @@ class MachineRegisterInfo { (private) } /// def_iterator/def_begin/def_end - Walk all defs of the specified register. - typedef defusechain_iterator - def_iterator; + using def_iterator = + defusechain_iterator; def_iterator def_begin(unsigned RegNo) const { return def_iterator(getRegUseDefListHead(RegNo)); } @@ -382,8 +384,8 @@ class MachineRegisterInfo { (private) /// def_instr_iterator/def_instr_begin/def_instr_end - Walk all defs of the /// specified register, stepping by MachineInst. - typedef defusechain_instr_iterator - def_instr_iterator; + using def_instr_iterator = + defusechain_instr_iterator; def_instr_iterator def_instr_begin(unsigned RegNo) const { return def_instr_iterator(getRegUseDefListHead(RegNo)); } @@ -398,8 +400,8 @@ class MachineRegisterInfo { (private) /// def_bundle_iterator/def_bundle_begin/def_bundle_end - Walk all defs of the /// specified register, stepping by bundle. - typedef defusechain_instr_iterator - def_bundle_iterator; + using def_bundle_iterator = + defusechain_instr_iterator; def_bundle_iterator def_bundle_begin(unsigned RegNo) const { return def_bundle_iterator(getRegUseDefListHead(RegNo)); } @@ -425,8 +427,8 @@ class MachineRegisterInfo { (private) } /// use_iterator/use_begin/use_end - Walk all uses of the specified register. - typedef defusechain_iterator - use_iterator; + using use_iterator = + defusechain_iterator; use_iterator use_begin(unsigned RegNo) const { return use_iterator(getRegUseDefListHead(RegNo)); } @@ -438,8 +440,8 @@ class MachineRegisterInfo { (private) /// use_instr_iterator/use_instr_begin/use_instr_end - Walk all uses of the /// specified register, stepping by MachineInstr. - typedef defusechain_instr_iterator - use_instr_iterator; + using use_instr_iterator = + defusechain_instr_iterator; use_instr_iterator use_instr_begin(unsigned RegNo) const { return use_instr_iterator(getRegUseDefListHead(RegNo)); } @@ -454,8 +456,8 @@ class MachineRegisterInfo { (private) /// use_bundle_iterator/use_bundle_begin/use_bundle_end - Walk all uses of the /// specified register, stepping by bundle. - typedef defusechain_instr_iterator - use_bundle_iterator; + using use_bundle_iterator = + defusechain_instr_iterator; use_bundle_iterator use_bundle_begin(unsigned RegNo) const { return use_bundle_iterator(getRegUseDefListHead(RegNo)); } @@ -482,8 +484,8 @@ class MachineRegisterInfo { (private) /// use_nodbg_iterator/use_nodbg_begin/use_nodbg_end - Walk all uses of the /// specified register, skipping those marked as Debug. - typedef defusechain_iterator - use_nodbg_iterator; + using use_nodbg_iterator = + defusechain_iterator; use_nodbg_iterator use_nodbg_begin(unsigned RegNo) const { return use_nodbg_iterator(getRegUseDefListHead(RegNo)); } @@ -499,8 +501,8 @@ class MachineRegisterInfo { (private) /// use_instr_nodbg_iterator/use_instr_nodbg_begin/use_instr_nodbg_end - Walk /// all uses of the specified register, stepping by MachineInstr, skipping /// those marked as Debug. - typedef defusechain_instr_iterator - use_instr_nodbg_iterator; + using use_instr_nodbg_iterator = + defusechain_instr_iterator; use_instr_nodbg_iterator use_instr_nodbg_begin(unsigned RegNo) const { return use_instr_nodbg_iterator(getRegUseDefListHead(RegNo)); } @@ -516,8 +518,8 @@ class MachineRegisterInfo { (private) /// use_bundle_nodbg_iterator/use_bundle_nodbg_begin/use_bundle_nodbg_end - Walk /// all uses of the specified register, stepping by bundle, skipping /// those marked as Debug. - typedef defusechain_instr_iterator - use_bundle_nodbg_iterator; + using use_bundle_nodbg_iterator = + defusechain_instr_iterator; use_bundle_nodbg_iterator use_bundle_nodbg_begin(unsigned RegNo) const { return use_bundle_nodbg_iterator(getRegUseDefListHead(RegNo)); } @@ -593,7 +595,6 @@ class MachineRegisterInfo { (private) /// Return the register class of the specified virtual register. /// This shouldn't be used directly unless \p Reg has a register class. /// \see getRegClassOrNull when this might happen. - /// const TargetRegisterClass *getRegClass(unsigned Reg) const { assert(VRegInfo[Reg].first.is() && "Register class not set, wrong accessor"); @@ -620,7 +621,6 @@ class MachineRegisterInfo { (private) /// a register bank or has been assigned a register class. /// \note It is possible to get the register bank from the register class via /// RegisterBankInfo::getRegBankFromRegClass. - /// const RegisterBank *getRegBankOrNull(unsigned Reg) const { const RegClassOrRegBank &Val = VRegInfo[Reg].first; return Val.dyn_cast(); @@ -629,17 +629,14 @@ class MachineRegisterInfo { (private) /// Return the register bank or register class of \p Reg. /// \note Before the register bank gets assigned (i.e., before the /// RegBankSelect pass) \p Reg may not have either. - /// const RegClassOrRegBank &getRegClassOrRegBank(unsigned Reg) const { return VRegInfo[Reg].first; } /// setRegClass - Set the register class of the specified virtual register. - /// void setRegClass(unsigned Reg, const TargetRegisterClass *RC); /// Set the register bank to \p RegBank for \p Reg. - /// void setRegBank(unsigned Reg, const RegisterBank &RegBank); void setRegClassOrRegBank(unsigned Reg, @@ -653,7 +650,6 @@ class MachineRegisterInfo { (private) /// new register class, or NULL if no such class exists. /// This should only be used when the constraint is known to be trivial, like /// GR32 -> GR32_NOSP. Beware of increasing register pressure. - /// const TargetRegisterClass *constrainRegClass(unsigned Reg, const TargetRegisterClass *RC, unsigned MinNumRegs = 0); @@ -665,12 +661,10 @@ class MachineRegisterInfo { (private) /// This method can be used after constraints have been removed from a /// virtual register, for example after removing instructions or splitting /// the live range. - /// bool recomputeRegClass(unsigned Reg); /// createVirtualRegister - Create and return a new virtual register in the /// function with the specified register class. - /// unsigned createVirtualRegister(const TargetRegisterClass *RegClass); /// Accessor for VRegToType. This accessor should only be used @@ -704,7 +698,6 @@ class MachineRegisterInfo { (private) unsigned createIncompleteVirtualRegister(); /// getNumVirtRegs - Return the number of virtual registers created. - /// unsigned getNumVirtRegs() const { return VRegInfo.size(); } /// clearVirtRegs - Remove all virtual registers (after physreg assignment). @@ -810,7 +803,6 @@ class MachineRegisterInfo { (private) /// /// Reserved registers may belong to an allocatable register class, but the /// target has explicitly requested that they are not used. - /// bool isReserved(unsigned PhysReg) const { return getReservedRegs().test(PhysReg); } @@ -838,8 +830,8 @@ class MachineRegisterInfo { (private) // Iteration support for the live-ins set. It's kept in sorted order // by register number. - typedef std::vector>::const_iterator - livein_iterator; + using livein_iterator = + std::vector>::const_iterator; livein_iterator livein_begin() const { return LiveIns.begin(); } livein_iterator livein_end() const { return LiveIns.end(); } bool livein_empty() const { return LiveIns.empty(); } @@ -910,10 +902,10 @@ class MachineRegisterInfo { (private) } public: - typedef std::iterator::reference reference; - typedef std::iterator::pointer pointer; + using reference = std::iterator::reference; + using pointer = std::iterator::pointer; defusechain_iterator() = default; @@ -1016,10 +1008,10 @@ class MachineRegisterInfo { (private) } public: - typedef std::iterator::reference reference; - typedef std::iterator::pointer pointer; + using reference = std::iterator::reference; + using pointer = std::iterator::pointer; defusechain_instr_iterator() = default; Modified: vendor/llvm/dist/include/llvm/CodeGen/MachineScheduler.h ============================================================================== --- vendor/llvm/dist/include/llvm/CodeGen/MachineScheduler.h Sat Jun 3 14:45:46 2017 (r319522) +++ vendor/llvm/dist/include/llvm/CodeGen/MachineScheduler.h Sat Jun 3 15:20:36 2017 (r319523) @@ -104,10 +104,15 @@ extern cl::opt ForceBottomUp; class LiveIntervals; class MachineDominatorTree; +class MachineFunction; +class MachineInstr; class MachineLoopInfo; class RegisterClassInfo; class SchedDFSResult; class ScheduleHazardRecognizer; +class TargetInstrInfo; +class TargetPassConfig; +class TargetRegisterInfo; /// MachineSchedContext provides enough context from the MachineScheduler pass /// for the target to instantiate a scheduler. @@ -129,10 +134,10 @@ struct MachineSchedContext { /// schedulers. class MachineSchedRegistry : public MachinePassRegistryNode { public: - typedef ScheduleDAGInstrs *(*ScheduleDAGCtor)(MachineSchedContext *); + using ScheduleDAGCtor = ScheduleDAGInstrs *(*)(MachineSchedContext *); // RegisterPassParser requires a (misnamed) FunctionPassCtor type. - typedef ScheduleDAGCtor FunctionPassCtor; + using FunctionPassCtor = ScheduleDAGCtor; static MachinePassRegistry Registry; @@ -527,7 +532,7 @@ class ReadyQueue { (public) unsigned size() const { return Queue.size(); } - typedef std::vector::iterator iterator; + using iterator = std::vector::iterator; iterator begin() { return Queue.begin(); } Modified: vendor/llvm/dist/include/llvm/CodeGen/PBQP/CostAllocator.h ============================================================================== --- vendor/llvm/dist/include/llvm/CodeGen/PBQP/CostAllocator.h Sat Jun 3 14:45:46 2017 (r319522) +++ vendor/llvm/dist/include/llvm/CodeGen/PBQP/CostAllocator.h Sat Jun 3 15:20:36 2017 (r319523) @@ -1,4 +1,4 @@ -//===---------- CostAllocator.h - PBQP Cost Allocator -----------*- C++ -*-===// +//===- CostAllocator.h - PBQP Cost Allocator --------------------*- C++ -*-===// // // The LLVM Compiler Infrastructure // @@ -19,26 +19,28 @@ #define LLVM_CODEGEN_PBQP_COSTALLOCATOR_H #include "llvm/ADT/DenseSet.h" +#include +#include #include -#include namespace llvm { namespace PBQP { -template -class ValuePool { +template class ValuePool { public: - typedef std::shared_ptr PoolRef; + using PoolRef = std::shared_ptr; private: - class PoolEntry : public std::enable_shared_from_this { public: template PoolEntry(ValuePool &Pool, ValueKeyT Value) : Pool(Pool), Value(std::move(Value)) {} + ~PoolEntry() { Pool.removeEntry(this); } - const ValueT& getValue() const { return Value; } + + const ValueT &getValue() const { return Value; } + private: ValuePool &Pool; ValueT Value; @@ -46,10 +48,10 @@ class ValuePool { (private) class PoolEntryDSInfo { public: - static inline PoolEntry* getEmptyKey() { return nullptr; } + static inline PoolEntry *getEmptyKey() { return nullptr; } - static inline PoolEntry* getTombstoneKey() { - return reinterpret_cast(static_cast(1)); + static inline PoolEntry *getTombstoneKey() { + return reinterpret_cast(static_cast(1)); } template @@ -66,8 +68,7 @@ class ValuePool { (private) } template - static - bool isEqual(const ValueKeyT1 &C1, const ValueKeyT2 &C2) { + static bool isEqual(const ValueKeyT1 &C1, const ValueKeyT2 &C2) { return C1 == C2; } @@ -83,10 +84,9 @@ class ValuePool { (private) return P1 == P2; return isEqual(P1->getValue(), P2); } - }; - typedef DenseSet EntrySetT; + using EntrySetT = DenseSet; EntrySetT EntrySet; @@ -105,28 +105,31 @@ class ValuePool { (private) } }; -template -class PoolCostAllocator { +template class PoolCostAllocator { private: - typedef ValuePool VectorCostPool; - typedef ValuePool MatrixCostPool; + using VectorCostPool = ValuePool; + using MatrixCostPool = ValuePool; + public: - typedef VectorT Vector; - typedef MatrixT Matrix; - typedef typename VectorCostPool::PoolRef VectorPtr; - typedef typename MatrixCostPool::PoolRef MatrixPtr; + using Vector = VectorT; + using Matrix = MatrixT; + using VectorPtr = typename VectorCostPool::PoolRef; + using MatrixPtr = typename MatrixCostPool::PoolRef; - template - VectorPtr getVector(VectorKeyT v) { return VectorPool.getValue(std::move(v)); } + template VectorPtr getVector(VectorKeyT v) { + return VectorPool.getValue(std::move(v)); + } - template - MatrixPtr getMatrix(MatrixKeyT m) { return MatrixPool.getValue(std::move(m)); } + template MatrixPtr getMatrix(MatrixKeyT m) { + return MatrixPool.getValue(std::move(m)); + } + private: VectorCostPool VectorPool; MatrixCostPool MatrixPool; }; -} // namespace PBQP -} // namespace llvm +} // end namespace PBQP +} // end namespace llvm -#endif +#endif // LLVM_CODEGEN_PBQP_COSTALLOCATOR_H Modified: vendor/llvm/dist/include/llvm/CodeGen/PBQP/Graph.h ============================================================================== --- vendor/llvm/dist/include/llvm/CodeGen/PBQP/Graph.h Sat Jun 3 14:45:46 2017 (r319522) +++ vendor/llvm/dist/include/llvm/CodeGen/PBQP/Graph.h Sat Jun 3 15:20:36 2017 (r319523) @@ -1,4 +1,4 @@ -//===-------------------- Graph.h - PBQP Graph ------------------*- C++ -*-===// +//===- Graph.h - PBQP Graph -------------------------------------*- C++ -*-===// // // The LLVM Compiler Infrastructure // @@ -11,16 +11,14 @@ // //===----------------------------------------------------------------------===// - #ifndef LLVM_CODEGEN_PBQP_GRAPH_H #define LLVM_CODEGEN_PBQP_GRAPH_H #include "llvm/ADT/STLExtras.h" -#include "llvm/Support/Debug.h" #include #include +#include #include -#include #include namespace llvm { @@ -28,8 +26,8 @@ namespace PBQP { class GraphBase { public: - typedef unsigned NodeId; - typedef unsigned EdgeId; + using NodeId = unsigned; + using EdgeId = unsigned; /// @brief Returns a value representing an invalid (non-existent) node. static NodeId invalidNodeId() { @@ -48,32 +46,32 @@ namespace PBQP { template class Graph : public GraphBase { private: - typedef typename SolverT::CostAllocator CostAllocator; + using CostAllocator = typename SolverT::CostAllocator; + public: - typedef typename SolverT::RawVector RawVector; - typedef typename SolverT::RawMatrix RawMatrix; - typedef typename SolverT::Vector Vector; - typedef typename SolverT::Matrix Matrix; - typedef typename CostAllocator::VectorPtr VectorPtr; - typedef typename CostAllocator::MatrixPtr MatrixPtr; - typedef typename SolverT::NodeMetadata NodeMetadata; - typedef typename SolverT::EdgeMetadata EdgeMetadata; - typedef typename SolverT::GraphMetadata GraphMetadata; + using RawVector = typename SolverT::RawVector; + using RawMatrix = typename SolverT::RawMatrix; + using Vector = typename SolverT::Vector; + using Matrix = typename SolverT::Matrix; + using VectorPtr = typename CostAllocator::VectorPtr; + using MatrixPtr = typename CostAllocator::MatrixPtr; + using NodeMetadata = typename SolverT::NodeMetadata; + using EdgeMetadata = typename SolverT::EdgeMetadata; + using GraphMetadata = typename SolverT::GraphMetadata; private: - class NodeEntry { public: - typedef std::vector AdjEdgeList; - typedef AdjEdgeList::size_type AdjEdgeIdx; - typedef AdjEdgeList::const_iterator AdjEdgeItr; + using AdjEdgeList = std::vector; + using AdjEdgeIdx = AdjEdgeList::size_type; + using AdjEdgeItr = AdjEdgeList::const_iterator; + NodeEntry(VectorPtr Costs) : Costs(std::move(Costs)) {} + static AdjEdgeIdx getInvalidAdjEdgeIdx() { return std::numeric_limits::max(); } - NodeEntry(VectorPtr Costs) : Costs(std::move(Costs)) {} - AdjEdgeIdx addAdjEdgeId(EdgeId EId) { AdjEdgeIdx Idx = AdjEdgeIds.size(); AdjEdgeIds.push_back(EId); @@ -96,6 +94,7 @@ namespace PBQP { VectorPtr Costs; NodeMetadata Metadata; + private: AdjEdgeList AdjEdgeIds; }; @@ -150,8 +149,10 @@ namespace PBQP { NodeId getN1Id() const { return NIds[0]; } NodeId getN2Id() const { return NIds[1]; } + MatrixPtr Costs; EdgeMetadata Metadata; + private: NodeId NIds[2]; typename NodeEntry::AdjEdgeIdx ThisEdgeAdjIdxs[2]; @@ -161,18 +162,20 @@ namespace PBQP { GraphMetadata Metadata; CostAllocator CostAlloc; - SolverT *Solver; + SolverT *Solver = nullptr; - typedef std::vector NodeVector; - typedef std::vector FreeNodeVector; + using NodeVector = std::vector; + using FreeNodeVector = std::vector; NodeVector Nodes; FreeNodeVector FreeNodeIds; - typedef std::vector EdgeVector; - typedef std::vector FreeEdgeVector; + using EdgeVector = std::vector; + using FreeEdgeVector = std::vector; EdgeVector Edges; FreeEdgeVector FreeEdgeIds; + Graph(const Graph &Other) {} + // ----- INTERNAL METHODS ----- NodeEntry &getNode(NodeId NId) { @@ -220,20 +223,18 @@ namespace PBQP { return EId; } - Graph(const Graph &Other) {} void operator=(const Graph &Other) {} public: + using AdjEdgeItr = typename NodeEntry::AdjEdgeItr; - typedef typename NodeEntry::AdjEdgeItr AdjEdgeItr; - class NodeItr { public: - typedef std::forward_iterator_tag iterator_category; - typedef NodeId value_type; - typedef int difference_type; - typedef NodeId* pointer; - typedef NodeId& reference; + using iterator_category = std::forward_iterator_tag; + using value_type = NodeId; + using difference_type = int; + using pointer = NodeId *; + using reference = NodeId &; NodeItr(NodeId CurNId, const Graph &G) : CurNId(CurNId), EndNId(G.Nodes.size()), FreeNodeIds(G.FreeNodeIds) { @@ -283,53 +284,65 @@ namespace PBQP { class NodeIdSet { public: - NodeIdSet(const Graph &G) : G(G) { } + NodeIdSet(const Graph &G) : G(G) {} + NodeItr begin() const { return NodeItr(0, G); } NodeItr end() const { return NodeItr(G.Nodes.size(), G); } + bool empty() const { return G.Nodes.empty(); } + typename NodeVector::size_type size() const { return G.Nodes.size() - G.FreeNodeIds.size(); } + private: const Graph& G; }; class EdgeIdSet { public: - EdgeIdSet(const Graph &G) : G(G) { } + EdgeIdSet(const Graph &G) : G(G) {} + EdgeItr begin() const { return EdgeItr(0, G); } EdgeItr end() const { return EdgeItr(G.Edges.size(), G); } + bool empty() const { return G.Edges.empty(); } + typename NodeVector::size_type size() const { return G.Edges.size() - G.FreeEdgeIds.size(); } + private: const Graph& G; }; class AdjEdgeIdSet { public: - AdjEdgeIdSet(const NodeEntry &NE) : NE(NE) { } + AdjEdgeIdSet(const NodeEntry &NE) : NE(NE) {} + typename NodeEntry::AdjEdgeItr begin() const { return NE.getAdjEdgeIds().begin(); } + typename NodeEntry::AdjEdgeItr end() const { return NE.getAdjEdgeIds().end(); } + bool empty() const { return NE.getAdjEdgeIds().empty(); } + typename NodeEntry::AdjEdgeList::size_type size() const { return NE.getAdjEdgeIds().size(); } + private: const NodeEntry &NE; }; /// @brief Construct an empty PBQP graph. - Graph() : Solver(nullptr) {} + Graph() = default; /// @brief Construct an empty PBQP graph with the given graph metadata. - Graph(GraphMetadata Metadata) - : Metadata(std::move(Metadata)), Solver(nullptr) {} + Graph(GraphMetadata Metadata) : Metadata(std::move(Metadata)) {} *** DIFF OUTPUT TRUNCATED AT 1000 LINES ***