Date: Thu, 27 Jul 2006 15:56:01 GMT From: Olivier Houchard <cognet@FreeBSD.org> To: Perforce Change Reviews <perforce@freebsd.org> Subject: PERFORCE change 102564 for review Message-ID: <200607271556.k6RFu19B087811@repoman.freebsd.org>
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http://perforce.freebsd.org/chv.cgi?CH=102564 Change 102564 by cognet@cognet on 2006/07/27 15:55:15 New toolchain patchset : this one moves all the modified bits from contrib/ to gnu/, as patches or new files, so contrib-arm.diff is no longer needed. I tested it and was able to produce both LE and BE worlds. It should just be applied to the userland bits in this branch, but I have no time to do that right now. Affected files ... .. //depot/projects/arm/contrib-arm.diff#7 delete .. //depot/projects/arm/gnu-arm.diff#18 edit Differences ... ==== //depot/projects/arm/gnu-arm.diff#18 (text+ko) ==== @@ -93,59 +93,131 @@ +#include "tc-arm.h" Index: gnu/usr.bin/binutils/ld/Makefile.arm =================================================================== -RCS file: gnu/usr.bin/binutils/ld/Makefile.arm -diff -N gnu/usr.bin/binutils/ld/Makefile.arm ---- ld.orig/Makefile.arm Tue Jul 25 11:25:14 2006 -+++ ld/Makefile.arm Tue Jul 25 11:27:44 2006 -@@ -1,6 +1,10 @@ +RCS file: /cognet/ncvs/src/gnu/usr.bin/binutils/ld/Makefile.arm,v +retrieving revision 1.1 +diff -u -p -r1.1 Makefile.arm +--- gnu/usr.bin/binutils/ld/Makefile.arm 22 Jul 2006 14:36:15 -0000 1.1 ++++ gnu/usr.bin/binutils/ld/Makefile.arm 26 Jul 2006 21:47:53 -0000 +@@ -1,12 +1,17 @@ # $FreeBSD: src/gnu/usr.bin/binutils/ld/Makefile.arm,v 1.1 2006/07/22 14:36:15 obrien Exp $ +-NATIVE_EMULATION= armelf_fbsd +.if defined(ARM_BIG_ENDIAN) -+NATIVE_EMULATION= armelfb_fbsd ++NATIVE_EMULATION= armelfb_fbsd +.else - NATIVE_EMULATION= armelf_fbsd ++NATIVE_EMULATION= armelf_fbsd +.endif SRCS+= e${NATIVE_EMULATION}.c CLEANFILES+= e${NATIVE_EMULATION}.c +-e${NATIVE_EMULATION}.c: emulparams/${NATIVE_EMULATION}.sh emultempl/elf32.em \ ++e${NATIVE_EMULATION}.c: ${.CURDIR}/${NATIVE_EMULATION}.sh emultempl/elf32.em \ + scripttempl/elf.sc genscripts.sh stringify.sed + sh ${.CURDIR}/genscripts.sh ${SRCDIR}/ld ${LIBSERACHPATH} \ + ${TOOLS_PREFIX}/usr \ + ${HOST} ${TARGET_TUPLE} ${TARGET_TUPLE} \ +- ${NATIVE_EMULATION} "" no ${NATIVE_EMULATION} ${TARGET_TUPLE} ++ ${NATIVE_EMULATION} "" no ${NATIVE_EMULATION} ${TARGET_TUPLE} \ ++ ${.CURDIR}/${NATIVE_EMULATION}.sh +Index: gnu/usr.bin/binutils/ld/armelf_fbsd.sh +=================================================================== +RCS file: gnu/usr.bin/binutils/ld/armelf_fbsd.sh +diff -N gnu/usr.bin/binutils/ld/armelf_fbsd.sh +--- /dev/null 1 Jan 1970 00:00:00 -0000 ++++ gnu/usr.bin/binutils/ld/armelf_fbsd.sh 26 Jul 2006 17:41:39 -0000 +@@ -0,0 +1,7 @@ ++. ${srcdir}/emulparams/armelf.sh ++. ${srcdir}/emulparams/elf_fbsd.sh ++MAXPAGESIZE=0x8000 ++GENERATE_PIE_SCRIPT=yes ++ ++unset STACK_ADDR ++unset EMBEDDED +Index: gnu/usr.bin/binutils/ld/armelfb_fbsd.sh +=================================================================== +RCS file: gnu/usr.bin/binutils/ld/armelfb_fbsd.sh +diff -N gnu/usr.bin/binutils/ld/armelfb_fbsd.sh +--- /dev/null 1 Jan 1970 00:00:00 -0000 ++++ gnu/usr.bin/binutils/ld/armelfb_fbsd.sh 27 Jul 2006 15:06:29 -0000 +@@ -0,0 +1,12 @@ ++#XXX: This should be used once those bits are merged back in the FSF repo. ++#. ${srcdir}/emulparams/armelf_fbsd.sh ++# ++#OUTPUT_FORMAT="elf32-bigarm" ++. ${srcdir}/emulparams/armelf.sh ++. ${srcdir}/emulparams/elf_fbsd.sh ++MAXPAGESIZE=0x8000 ++GENERATE_PIE_SCRIPT=yes ++ ++unset STACK_ADDR ++unset EMBEDDED ++OUTPUT_FORMAT="elf32-bigarm" +Index: gnu/usr.bin/binutils/ld/genscripts.sh +=================================================================== +RCS file: /cognet/ncvs/src/gnu/usr.bin/binutils/ld/genscripts.sh,v +retrieving revision 1.6 +diff -u -p -r1.6 genscripts.sh +--- gnu/usr.bin/binutils/ld/genscripts.sh 16 Jun 2004 07:09:37 -0000 1.6 ++++ gnu/usr.bin/binutils/ld/genscripts.sh 26 Jul 2006 21:52:04 -0000 +@@ -37,7 +37,12 @@ CUSTOMIZER_SCRIPT=$3 + # FSF BU ver 2.15 which allows for a more generic emulparams processing. + # To reduce the diff, I also include the ${EMULATION_NAME} parameter in uses + # of 'CUSTOMIZER_SCRIPT'. ++ ++# XXX: arm hack : until those file are merged back into the FSF repo, just ++# use the version in this directory. ++if !(test -f ${CUSTOMIZER_SCRIPT}"";) then + CUSTOMIZER_SCRIPT="${srcdir}/emulparams/${EMULATION_NAME}.sh" ++fi + + # Include the emulation-specific parameters: + . ${CUSTOMIZER_SCRIPT} ${EMULATION_NAME} Index: gnu/usr.bin/binutils/libbfd/Makefile.arm =================================================================== -RCS file: gnu/usr.bin/binutils/libbfd/Makefile.arm -diff -N gnu/usr.bin/binutils/libbfd/Makefile.arm ---- gnu/usr.bin/binutils/libbfd.orig/Makefile.arm Tue Jul 25 10:59:44 2006 -+++ gnu/usr.bin/binutils/libbfd/Makefile.arm Tue Jul 25 10:58:56 2006 -@@ -1,14 +1,47 @@ +RCS file: /cognet/ncvs/src/gnu/usr.bin/binutils/libbfd/Makefile.arm,v +retrieving revision 1.2 +diff -u -p -r1.2 Makefile.arm +--- gnu/usr.bin/binutils/libbfd/Makefile.arm 22 Jul 2006 14:55:55 -0000 1.2 ++++ gnu/usr.bin/binutils/libbfd/Makefile.arm 24 Jul 2006 20:55:48 -0000 +@@ -1,14 +1,52 @@ # $FreeBSD: src/gnu/usr.bin/binutils/libbfd/Makefile.arm,v 1.2 2006/07/22 14:55:55 obrien Exp $ --DEFAULT_VECTOR= bfd_elf32_littlearm_vec +.if defined(ARM_BIG_ENDIAN) +DEFAULT_VECTOR= bfd_elf32_bigarm_vec +ADDITIONAL_VECTOR= bfd_elf32_littlearm_vec +.else -+DEFAULT_VECTOR= bfd_elf32_littlearm_vec + DEFAULT_VECTOR= bfd_elf32_littlearm_vec +ADDITIONAL_VECTOR= bfd_elf32_bigarm_vec +.endif - SRCS+= cpu-arm.c \ - elf32.c \ +-SRCS+= cpu-arm.c \ +- elf32.c \ ++SRCS+= \ ++ cpu-arm.c \ ++ elf32.c \ elf32-arm-fbsd.c \ - elf32-gen.c \ +- elf32-gen.c \ - elf32-target.h - elfarm-nabi.c \ +- elflink.c ++ elf32-gen.c \ + elf32-target.h \ -+ elfarm-oabi.c \ - elflink.c ++ elflink.c ++VECS+= ${DEFAULT_VECTOR} \ ++ ${ADDITIONAL_VECTOR} - VECS= ${DEFAULT_VECTOR} \ +-VECS= ${DEFAULT_VECTOR} \ - bfd_elf32_bigarm_vec -+ ${ADDITIONAL_VECTOR} -+ +.if ${TARGET_ARCH} == "arm" +CFLAGS+= -DDEFAULT_VECTOR=${DEFAULT_VECTOR} +.endif + -+CLEANFILES+= elf32-arm-fbsd.c ++CLEANFILES+= elf32-arm-fbsd.c + ++# ++# XXX: We should really add the FreeBSD case in elf32_arm_nabi_grok_prstatus ++# instead of defining our own elf32_fbsd_arm_grok_prstatus. ++# +elf32-arm-fbsd.c: elfarm-nabi.c + cat ${.ALLSRC} | sed -e s/ELFOSABI_ARM/ELFOSABI_FREEBSD/g \ + -e "s/\(.*#define.*\)elf32_arm_nabi_grok_prstatus/\1elf32_fbsd_arm_grok_prstatus/" -e s/"#include.*elf32-arm.h.*//" >${.TARGET}; \ @@ -156,17 +228,18 @@ + int offset; \ + if (note->descsz != 96) \ + return (FALSE); \ -+ offset = 28; \ -+ raw_size = 68; \ -+ if (elf_tdata(abfd)->core_signal == 0) \ -+ elf_tdata (abfd)->core_signal = ((int *)(note->descdata))[5]; \ -+ elf_tdata (abfd)->core_pid = ((int *)(note->descdata))[6]; \ -+ /* Make a ".reg/999" section. */ \ -+ return _bfd_elfcore_make_pseudosection (abfd, ".reg", \ -+ raw_size, note->descpos + offset); \ -+ }' >> ${.TARGET}; \ ++ offset = 28; \ ++ raw_size = 68; \ ++ if (elf_tdata(abfd)->core_signal == 0) \ ++ elf_tdata (abfd)->core_signal = ((int *)(note->descdata))[5]; \ ++ elf_tdata (abfd)->core_pid = ((int *)(note->descdata))[6]; \ ++ /* Make a ".reg/999" section. */ \ ++ return _bfd_elfcore_make_pseudosection (abfd, ".reg", \ ++ raw_size, note->descpos + offset); \ ++}' >> ${.TARGET}; \ + echo '#include "elf32-arm.h"' >> ${.TARGET} - ++ ++ Index: gnu/usr.bin/binutils/libiberty/Makefile =================================================================== RCS file: /cognet/ncvs/src/gnu/usr.bin/binutils/libiberty/Makefile,v @@ -208,17 +281,97 @@ #define HOST_WORDS_BIG_ENDIAN 1 #endif -Index: gnu/usr.bin/binutils/libopcodes/Makefile.arm +Index: gnu/usr.bin/cc/Makefile.inc +=================================================================== +RCS file: /cognet/ncvs/src/gnu/usr.bin/cc/Makefile.inc,v +retrieving revision 1.63 +diff -u -p -r1.63 Makefile.inc +--- gnu/usr.bin/cc/Makefile.inc 4 Jun 2002 19:45:08 -0000 1.63 ++++ gnu/usr.bin/cc/Makefile.inc 26 Jul 2006 21:44:41 -0000 +@@ -11,7 +11,11 @@ GCCDIR= ${.CURDIR}/../../../../contrib/g + .include "Makefile.tgt" + + # Machine description. ++.if ${TARGET_ARCH} == "arm" ++MD_FILE= ${.OBJDIR}/arm-diked.md ++.else + MD_FILE= ${GCCDIR}/config/${GCC_CPU}/${GCC_CPU}.md ++.endif + target= ${TARGET_ARCH}-undermydesk-freebsd + + CFLAGS+= -DIN_GCC -DHAVE_CONFIG_H +@@ -47,3 +51,17 @@ LIBCC_INT= ${.CURDIR}/../cc_int/libcc_in + .endif + + .endif # !__CC_MAKEFILE_INC__ ++.if ${TARGET_ARCH} == "arm" ++CLEANFILES+= arm-diked.md ${GCC_CPU}.md.orig fpa.md cirrus.md iwmmxt.md ++.endif ++ ++.if ${TARGET_ARCH} == "arm" ++${.OBJDIR}/arm-diked.md: ++ cp ${GCCDIR}/config/${GCC_CPU}/${GCC_CPU}.md . ++#XXX: Those are not patched but are included by arm.md ++ cp ${GCCDIR}/config/${GCC_CPU}/fpa.md . ++ cp ${GCCDIR}/config/${GCC_CPU}/cirrus.md . ++ cp ${GCCDIR}/config/${GCC_CPU}/iwmmxt.md . ++ patch ${GCC_CPU}.md ${.CURDIR}/../arm.md.diff ++ mv ${GCC_CPU}.md ${.TARGET} ++.endif +Index: gnu/usr.bin/cc/arm.md.diff =================================================================== -RCS file: gnu/usr.bin/binutils/libopcodes/Makefile.arm -diff -N gnu/usr.bin/binutils/libopcodes/Makefile.arm +RCS file: gnu/usr.bin/cc/arm.md.diff +diff -N gnu/usr.bin/cc/arm.md.diff --- /dev/null 1 Jan 1970 00:00:00 -0000 -+++ gnu/usr.bin/binutils/libopcodes/Makefile.arm 6 Jul 2006 23:54:06 -0000 -@@ -0,0 +1,4 @@ -+# $FreeBSD$ -+ -+SRCS+= arm-dis.c -+CFLAGS+= -DARCH_arm ++++ gnu/usr.bin/cc/arm.md.diff 24 Jul 2006 21:44:46 -0000 +@@ -0,0 +1,47 @@ ++Index: arm.md ++=================================================================== ++RCS file: /cognet/ncvs/src/contrib/gcc/config/arm/arm.md,v ++retrieving revision 1.1.1.7 ++diff -u -p -r1.1.1.7 arm.md ++--- arm.md 3 Jun 2005 03:28:42 -0000 1.1.1.7 +++++ arm.md 29 Aug 2005 12:39:39 -0000 ++@@ -8836,12 +8836,12 @@ ++ ldm[2] = operands[4]; ++ } ++ if (GET_CODE (XEXP (operands[2], 0)) != REG) ++- val1 = INTVAL (XEXP (XEXP (operands[2], 0), 1)); +++ val1 = INTVAL (XEXP (XEXP (operands[2], 0), 1)); ++ if (GET_CODE (XEXP (operands[3], 0)) != REG) ++- val2 = INTVAL (XEXP (XEXP (operands[3], 0), 1)); +++ val2 = INTVAL (XEXP (XEXP (operands[3], 0), 1)); ++ arith[0] = operands[0]; ++ arith[3] = operands[1]; ++- if (val1 < val2) +++ if (val1 <= val2) ++ { ++ arith[1] = ldm[1]; ++ arith[2] = ldm[2]; ++@@ -8871,7 +8871,7 @@ ++ else ++ output_asm_insn (\"ldm%?ia\\t%0, {%1, %2}\", ldm); ++ } ++- else +++ else if (val2) ++ { ++ ldm[0] = XEXP (operands[2], 0); ++ if (val1 < val2) ++@@ -8879,6 +8879,14 @@ ++ else ++ output_asm_insn (\"ldm%?da\\t%0, {%1, %2}\", ldm); ++ } +++ else { +++ ldm[0] = operands[0]; +++ ldm[1] = XEXP(operands[2], 0); +++ output_asm_insn(\"ldr\\t%0, [%1]\", ldm); +++ ldm[0] = operands[4]; +++ ldm[1] = XEXP(operands[3], 0); +++ output_asm_insn(\"ldr\\t%0, [%1]\", ldm); +++ } ++ output_asm_insn (\"%I3%?\\t%0, %1, %2\", arith); ++ return \"\"; ++ }" Index: gnu/usr.bin/cc/cc_int/Makefile =================================================================== RCS file: /cognet/ncvs/src/gnu/usr.bin/cc/cc_int/Makefile,v @@ -243,7 +396,7 @@ retrieving revision 1.82 diff -u -p -r1.82 Makefile --- gnu/usr.bin/cc/cc_tools/Makefile 17 Mar 2006 18:54:23 -0000 1.82 -+++ gnu/usr.bin/cc/cc_tools/Makefile 21 Jul 2006 11:15:28 -0000 ++++ gnu/usr.bin/cc/cc_tools/Makefile 27 Jul 2006 12:34:46 -0000 @@ -216,7 +216,9 @@ CLEANFILES+= fini .if ${TARGET_ARCH} == "amd64" TARGET_INC= i386/biarch64.h @@ -254,7 +407,7 @@ .if ${TARGET_ARCH} == "i386" || ${TARGET_ARCH} == "amd64" TARGET_INC+= ${GCC_CPU}/unix.h TARGET_INC+= ${GCC_CPU}/att.h -@@ -236,6 +238,14 @@ TARGET_INC+= ${GCC_CPU}/elf.h +@@ -236,7 +238,19 @@ TARGET_INC+= ${GCC_CPU}/elf.h TARGET_INC+= ${GCC_CPU}/sysv4.h .endif .endif @@ -266,16 +419,185 @@ +CFLAGS+= -DTARGET_ENDIAN_DEFAULT=ARM_FLAG_BIG_END +. endif +.endif ++.if ${TARGET_ARCH} == "arm" ++TARGET_INC+= freebsd-diked.h ++.else TARGET_INC+= ${GCC_CPU}/freebsd.h ++.endif .if ${TARGET_ARCH} == "amd64" TARGET_INC+= ${GCC_CPU}/x86-64.h + TARGET_INC+= ${GCC_CPU}/freebsd64.h +@@ -334,6 +348,10 @@ COMMONHDRS= bconfig.h config.h configarg + gtyp-gen.h + GENSRCS+= ${COMMONHDRS} + ++.if ${TARGET_ARCH} == "arm" ++GENSRCS+= freebsd-diked.h ++.endif ++ + MFILE?= ${.CURDIR}/Makefile + ${COMMONHDRS}: ${MFILE} + +@@ -389,7 +407,11 @@ specs.h: + config.h: bconfig.h + echo '#include <bconfig.h>' > ${.TARGET} + ++.if ${TARGET_ARCH} == "arm" ++tm.h: freebsd-diked.h ++.else + tm.h: ++.endif + echo '#ifndef GCC_TM_H' > ${.TARGET} + echo '#define GCC_TM_H' >> ${.TARGET} + .if defined(TARGET_CPU_DEFAULT) +@@ -458,12 +480,23 @@ gtyp-gen.h: + gcov-iov.h: + echo "#define GCOV_VERSION ((gcov_unsigned_t)0x33303470)" >> ${.TARGET} + ++.if ${TARGET_ARCH} == "arm" ++freebsd-diked.h: ++ cp ${GCCDIR}/config/arm/freebsd.h freebsd.h ++ patch freebsd.h ${GCCDIR}/../../gnu/usr.bin/cc/cc_tools/arm-freebsd.h.diff ++ mv freebsd.h ${.TARGET} ++.endif ++ + #----------------------------------------------------------------------- + # General things. + + SRCS+= ${GENSRCS} + CLEANFILES+= ${GENSRCS} + ++.if ${TARGET_ARCH} == "arm" ++CLEANFILES+= freebsd.h.orig ++.endif ++ + all: ${SRCS} + + .include <bsd.prog.mk> +Index: gnu/usr.bin/cc/cc_tools/arm-freebsd.h.diff +=================================================================== +RCS file: gnu/usr.bin/cc/cc_tools/arm-freebsd.h.diff +diff -N gnu/usr.bin/cc/cc_tools/arm-freebsd.h.diff +--- /dev/null 1 Jan 1970 00:00:00 -0000 ++++ gnu/usr.bin/cc/cc_tools/arm-freebsd.h.diff 24 Jul 2006 21:33:40 -0000 +@@ -0,0 +1,110 @@ ++Index: freebsd.h ++=================================================================== ++RCS file: /cognet/ncvs/src/contrib/gcc/config/arm/freebsd.h,v ++retrieving revision 1.1.1.3 ++diff -u -p -r1.1.1.3 freebsd.h ++--- freebsd.h 28 Jul 2004 03:11:35 -0000 1.1.1.3 +++++ freebsd.h 21 Jul 2006 00:50:25 -0000 ++@@ -22,7 +22,10 @@ ++ ++ #undef SUBTARGET_EXTRA_SPECS ++ #define SUBTARGET_EXTRA_SPECS \ ++- { "fbsd_dynamic_linker", FBSD_DYNAMIC_LINKER } +++ { "fbsd_dynamic_linker", FBSD_DYNAMIC_LINKER }, \ +++ { "subtarget_extra_asm_spec", SUBTARGET_EXTRA_ASM_SPEC }, \ +++ { "subtarget_asm_float_spec", SUBTARGET_ASM_FLOAT_SPEC } +++ ++ ++ #undef SUBTARGET_CPP_SPEC ++ #define SUBTARGET_CPP_SPEC FBSD_CPP_SPEC ++@@ -39,7 +42,8 @@ ++ %{rdynamic:-export-dynamic} \ ++ %{!dynamic-linker:-dynamic-linker %(fbsd_dynamic_linker) }} \ ++ %{static:-Bstatic}} \ ++- %{symbolic:-Bsymbolic}" +++ %{symbolic:-Bsymbolic} \ +++ %{mbig-endian:-EB} %{mlittle-endian:-EL}" ++ ++ ++ /************************[ Target stuff ]***********************************/ ++@@ -67,3 +71,80 @@ ++ ++ #undef TARGET_VERSION ++ #define TARGET_VERSION fprintf (stderr, " (FreeBSD/StrongARM ELF)"); +++ +++#ifndef TARGET_ENDIAN_DEFAULT +++#define TARGET_ENDIAN_DEFAULT 0 +++#endif +++ +++#undef TARGET_DEFAULT +++#define TARGET_DEFAULT \ +++ (ARM_FLAG_APCS_32 \ +++ | ARM_FLAG_SOFT_FLOAT \ +++ | ARM_FLAG_APCS_FRAME \ +++ | ARM_FLAG_ATPCS \ +++ | ARM_FLAG_VFP \ +++ | ARM_FLAG_MMU_TRAPS \ +++ | TARGET_ENDIAN_DEFAULT) +++ +++#undef TYPE_OPERAND_FMT +++#define TYPE_OPERAND_FMT "%%%s" +++ +++#undef SUBTARGET_EXTRA_ASM_SPEC +++#define SUBTARGET_EXTRA_ASM_SPEC \ +++ "-matpcs %{fpic|fpie:-k} %{fPIC|fPIE:-k}" +++ +++ /* Default floating point model is soft-VFP. +++ * FIXME: -mhard-float currently implies FPA. */ +++#undef SUBTARGET_ASM_FLOAT_SPEC +++#define SUBTARGET_ASM_FLOAT_SPEC \ +++ "%{mhard-float:-mfpu=fpa} \ +++ %{msoft-float:-mfpu=softvfp} \ +++ %{!mhard-float: \ +++ %{!msoft-float:-mfpu=softvfp}}" +++ +++ +++/* FreeBSD does its profiling differently to the Acorn compiler. We +++ don't need a word following the mcount call; and to skip it +++ requires either an assembly stub or use of fomit-frame-pointer when +++ compiling the profiling functions. Since we break Acorn CC +++ compatibility below a little more won't hurt. */ +++ +++#undef ARM_FUNCTION_PROFILER +++#define ARM_FUNCTION_PROFILER(STREAM,LABELNO) \ +++{ \ +++ asm_fprintf (STREAM, "\tmov\t%Rip, %Rlr\n"); \ +++ asm_fprintf (STREAM, "\tbl\t_mcount%s\n", \ +++ NEED_PLT_RELOC ? "(PLT)" : ""); \ +++} +++ +++/* Emit code to set up a trampoline and synchronize the caches. */ +++#undef INITIALIZE_TRAMPOLINE +++#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ +++do \ +++ { \ +++ emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 8)), \ +++ (CXT)); \ +++ emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 12)), \ +++ (FNADDR)); \ +++ emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__clear_cache"), \ +++ 0, VOIDmode, 2, TRAMP, Pmode, \ +++ plus_constant (TRAMP, TRAMPOLINE_SIZE), Pmode); \ +++ } \ +++while (0) +++ +++/* Clear the instruction cache from `BEG' to `END'. This makes a +++ call to the ARM_SYNC_ICACHE architecture specific syscall. */ +++#define CLEAR_INSN_CACHE(BEG, END) \ +++do \ +++ { \ +++ extern int sysarch(int number, void *args); \ +++ struct \ +++ { \ +++ unsigned int addr; \ +++ int len; \ +++ } s; \ +++ s.addr = (unsigned int)(BEG); \ +++ s.len = (END) - (BEG); \ +++ (void) sysarch (0, &s); \ +++ } \ +++while (0) Index: gnu/usr.bin/gdb/arch/arm/Makefile =================================================================== RCS file: gnu/usr.bin/gdb/arch/arm/Makefile diff -N gnu/usr.bin/gdb/arch/arm/Makefile --- /dev/null 1 Jan 1970 00:00:00 -0000 -+++ gnu/usr.bin/gdb/arch/arm/Makefile 7 Jul 2006 00:02:26 -0000 -@@ -0,0 +1,14 @@ ++++ gnu/usr.bin/gdb/arch/arm/Makefile 26 Jul 2006 17:56:49 -0000 +@@ -0,0 +1,17 @@ +# $FreeBSD$ + +GENSRCS+= xm.h @@ -283,20 +605,620 @@ +LIBSRCS+= arm-tdep.c armfbsd-tdep.c solib.c solib-svr4.c + +nm.h: -+ echo '#include "arm/nm-fbsd.h"' > ${.TARGET} ++#XXX this should be arm/nm-fbsd.h but won't until it's merged into the gdb repo ++ echo '#include "nm-fbsd.h"' > ${.TARGET} + +tm.h: -+ echo '#include "arm/tm-fbsd.h"' > ${.TARGET} ++#XXX this should be arm/tm-fbsd.h ++ echo '#include "tm-fbsd.h"' > ${.TARGET} + +xm.h: -+ echo '#include "arm/xm-fbsd.h"' > ${.TARGET} ++#XXX this should be arm/xm-fbsd.h ++ echo '#include "xm-fbsd.h"' > ${.TARGET} +Index: gnu/usr.bin/gdb/arch/arm/armfbsd-nat.c +=================================================================== +RCS file: gnu/usr.bin/gdb/arch/arm/armfbsd-nat.c +diff -N gnu/usr.bin/gdb/arch/arm/armfbsd-nat.c +--- /dev/null 1 Jan 1970 00:00:00 -0000 ++++ gnu/usr.bin/gdb/arch/arm/armfbsd-nat.c 19 Jul 2006 10:24:46 -0000 +@@ -0,0 +1,516 @@ ++ /* Native-dependent code for BSD Unix running on ARM's, for GDB. ++ Copyright 1988, 1989, 1991, 1992, 1994, 1996, 1999, 2002 ++ Free Software Foundation, Inc. ++ ++ This file is part of GDB. ++ ++ This program is free software; you can redistribute it and/or modify ++ it under the terms of the GNU General Public License as published by ++ the Free Software Foundation; either version 2 of the License, or ++ (at your option) any later version. ++ ++ This program is distributed in the hope that it will be useful, ++ but WITHOUT ANY WARRANTY; without even the implied warranty of ++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ GNU General Public License for more details. ++ ++ You should have received a copy of the GNU General Public License ++ along with this program; if not, write to the Free Software ++ Foundation, Inc., 59 Temple Place - Suite 330, ++ Boston, MA 02111-1307, USA. */ ++ ++#include "defs.h" ++ ++#ifndef FETCH_INFERIOR_REGISTERS ++#ifndef CROSS_DEBUGGER ++#error Not FETCH_INFERIOR_REGISTERS ++#endif ++#endif /* !FETCH_INFERIOR_REGISTERS */ ++ ++#include "arm-tdep.h" ++ ++#include <sys/types.h> ++#include <sys/ptrace.h> ++#ifndef CROSS_DEBUGGER ++#include <machine/reg.h> ++#include <machine/frame.h> ++#endif ++#include "inferior.h" ++#include "regcache.h" ++#include "gdbcore.h" ++ ++extern int arm_apcs_32; ++ ++#ifdef CROSS_DEBUGGER ++struct reg { ++ unsigned int r[13]; ++ unsigned int r_sp; ++ unsigned int r_lr; ++ unsigned int r_pc; ++ unsigned int r_cpsr; ++}; ++ ++typedef struct fp_extended_precision { ++ u_int32_t fp_exponent; ++ u_int32_t fp_mantissa_hi; ++ u_int32_t fp_mantissa_lo; ++} fp_extended_precision_t; ++ ++typedef struct fp_extended_precision fp_reg_t; ++ ++struct fpreg { ++ unsigned int fpr_fpsr; ++ fp_reg_t fpr[8]; ++}; ++#endif ++ ++void ++supply_gregset (struct reg *gregset) ++{ ++ int regno; ++ CORE_ADDR r_pc; ++ ++ /* Integer registers. */ ++ for (regno = ARM_A1_REGNUM; regno < ARM_SP_REGNUM; regno++) ++ supply_register (regno, (char *) &gregset->r[regno]); ++ ++ supply_register (ARM_SP_REGNUM, (char *) &gregset->r_sp); ++ supply_register (ARM_LR_REGNUM, (char *) &gregset->r_lr); ++ /* This is ok: we're running native... */ ++ r_pc = ADDR_BITS_REMOVE (gregset->r_pc); ++ supply_register (ARM_PC_REGNUM, (char *) &r_pc); ++ ++ if (arm_apcs_32) ++ supply_register (ARM_PS_REGNUM, (char *) &gregset->r_cpsr); ++ else ++ supply_register (ARM_PS_REGNUM, (char *) &gregset->r_pc); ++} ++ ++void ++supply_fpregset (struct fpreg *fparegset) ++{ ++ int regno; ++ ++ for (regno = ARM_F0_REGNUM; regno <= ARM_F7_REGNUM; regno++) ++ supply_register ++ (regno, (char *) &fparegset->fpr[regno - ARM_F0_REGNUM]); ++ ++ supply_register (ARM_FPS_REGNUM, (char *) &fparegset->fpr_fpsr); ++} ++ ++static void ++fetch_register (int regno) ++{ ++ struct reg inferior_registers; ++#ifndef CROSS_DEBUGGER ++ int ret; ++ ++ ret = ptrace (PT_GETREGS, PIDGET (inferior_ptid), ++ (PTRACE_ARG3_TYPE) &inferior_registers, 0); ++ ++ if (ret < 0) ++ { ++ warning ("unable to fetch general register"); ++ return; ++ } ++#endif ++ ++ switch (regno) ++ { ++ case ARM_SP_REGNUM: ++ supply_register (ARM_SP_REGNUM, (char *) &inferior_registers.r_sp); ++ break; ++ ++ case ARM_LR_REGNUM: ++ supply_register (ARM_LR_REGNUM, (char *) &inferior_registers.r_lr); ++ break; ++ ++ case ARM_PC_REGNUM: ++ /* This is ok: we're running native... */ ++ inferior_registers.r_pc = ADDR_BITS_REMOVE (inferior_registers.r_pc); ++ supply_register (ARM_PC_REGNUM, (char *) &inferior_registers.r_pc); ++ break; ++ ++ case ARM_PS_REGNUM: ++ if (arm_apcs_32) ++ supply_register (ARM_PS_REGNUM, (char *) &inferior_registers.r_cpsr); ++ else ++ supply_register (ARM_PS_REGNUM, (char *) &inferior_registers.r_pc); ++ break; ++ ++ default: ++ supply_register (regno, (char *) &inferior_registers.r[regno]); ++ break; ++ } ++} ++ ++static void ++fetch_regs (void) ++{ ++ struct reg inferior_registers; ++#ifndef CROSS_DEBUGGER ++ int ret; ++#endif ++ int regno; ++ ++#ifndef CROSS_DEBUGGER ++ ret = ptrace (PT_GETREGS, PIDGET (inferior_ptid), ++ (PTRACE_ARG3_TYPE) &inferior_registers, 0); ++ ++ if (ret < 0) ++ { ++ warning ("unable to fetch general registers"); ++ return; ++ } ++#endif ++ ++ supply_gregset (&inferior_registers); ++} ++ ++static void ++fetch_fp_register (int regno) ++{ ++ struct fpreg inferior_fp_registers; ++#ifndef CROSS_DEBUGGER ++ int ret; ++ ++ ret = ptrace (PT_GETFPREGS, PIDGET (inferior_ptid), ++ (PTRACE_ARG3_TYPE) &inferior_fp_registers, 0); ++ ++ if (ret < 0) ++ { ++ warning ("unable to fetch floating-point register"); ++ return; ++ } ++#endif ++ ++ switch (regno) ++ { ++ case ARM_FPS_REGNUM: ++ supply_register (ARM_FPS_REGNUM, ++ (char *) &inferior_fp_registers.fpr_fpsr); ++ break; ++ ++ default: ++ supply_register ++ (regno, (char *) &inferior_fp_registers.fpr[regno - ARM_F0_REGNUM]); ++ break; ++ } ++} ++ ++static void ++fetch_fp_regs (void) ++{ ++ struct fpreg inferior_fp_registers; ++#ifndef CROSS_DEBUGGER ++ int ret; ++#endif ++ int regno; ++ ++#ifndef CROSS_DEBUGGER ++ ret = ptrace (PT_GETFPREGS, PIDGET (inferior_ptid), ++ (PTRACE_ARG3_TYPE) &inferior_fp_registers, 0); ++ ++ if (ret < 0) ++ { ++ warning ("unable to fetch general registers"); ++ return; ++ } ++#endif ++ ++ supply_fpregset (&inferior_fp_registers); ++} ++ ++void ++fetch_inferior_registers (int regno) ++{ ++ if (regno >= 0) ++ { ++ if (regno < ARM_F0_REGNUM || regno > ARM_FPS_REGNUM) ++ fetch_register (regno); ++ else ++ fetch_fp_register (regno); ++ } ++ else ++ { ++ fetch_regs (); ++ fetch_fp_regs (); ++ } ++} ++ ++ ++static void ++store_register (int regno) ++{ ++ struct reg inferior_registers; ++#ifndef CROSS_DEBUGGER ++ int ret; ++ ++ ret = ptrace (PT_GETREGS, PIDGET (inferior_ptid), ++ (PTRACE_ARG3_TYPE) &inferior_registers, 0); ++ ++ if (ret < 0) ++ { ++ warning ("unable to fetch general registers"); ++ return; ++ } ++#endif ++ ++ switch (regno) ++ { ++ case ARM_SP_REGNUM: ++ regcache_collect (ARM_SP_REGNUM, (char *) &inferior_registers.r_sp); ++ break; ++ ++ case ARM_LR_REGNUM: ++ regcache_collect (ARM_LR_REGNUM, (char *) &inferior_registers.r_lr); ++ break; ++ ++ case ARM_PC_REGNUM: ++ if (arm_apcs_32) ++ regcache_collect (ARM_PC_REGNUM, (char *) &inferior_registers.r_pc); ++ else ++ { ++ unsigned pc_val; ++ ++ regcache_collect (ARM_PC_REGNUM, (char *) &pc_val); ++ ++ pc_val = ADDR_BITS_REMOVE (pc_val); ++ inferior_registers.r_pc ++ ^= ADDR_BITS_REMOVE (inferior_registers.r_pc); ++ inferior_registers.r_pc |= pc_val; ++ } ++ break; ++ ++ case ARM_PS_REGNUM: ++ if (arm_apcs_32) ++ regcache_collect (ARM_PS_REGNUM, (char *) &inferior_registers.r_cpsr); ++ else ++ { ++ unsigned psr_val; ++ ++ regcache_collect (ARM_PS_REGNUM, (char *) &psr_val); ++ ++ psr_val ^= ADDR_BITS_REMOVE (psr_val); ++ inferior_registers.r_pc = ADDR_BITS_REMOVE (inferior_registers.r_pc); ++ inferior_registers.r_pc |= psr_val; ++ } ++ break; ++ ++ default: ++ regcache_collect (regno, (char *) &inferior_registers.r[regno]); ++ break; ++ } ++ ++#ifndef CROSS_DEBUGGER ++ ret = ptrace (PT_SETREGS, PIDGET (inferior_ptid), ++ (PTRACE_ARG3_TYPE) &inferior_registers, 0); ++ ++ if (ret < 0) ++ warning ("unable to write register %d to inferior", regno); ++#endif ++} ++ ++static void ++store_regs (void) ++{ ++ struct reg inferior_registers; ++ int ret; ++ int regno; ++ ++ ++ for (regno = ARM_A1_REGNUM; regno < ARM_SP_REGNUM; regno++) ++ regcache_collect (regno, (char *) &inferior_registers.r[regno]); ++ ++ regcache_collect (ARM_SP_REGNUM, (char *) &inferior_registers.r_sp); ++ regcache_collect (ARM_LR_REGNUM, (char *) &inferior_registers.r_lr); ++ ++ if (arm_apcs_32) ++ { ++ regcache_collect (ARM_PC_REGNUM, (char *) &inferior_registers.r_pc); ++ regcache_collect (ARM_PS_REGNUM, (char *) &inferior_registers.r_cpsr); ++ } ++ else ++ { ++ unsigned pc_val; ++ unsigned psr_val; ++ ++ regcache_collect (ARM_PC_REGNUM, (char *) &pc_val); ++ regcache_collect (ARM_PS_REGNUM, (char *) &psr_val); ++ ++ pc_val = ADDR_BITS_REMOVE (pc_val); ++ psr_val ^= ADDR_BITS_REMOVE (psr_val); ++ ++ inferior_registers.r_pc = pc_val | psr_val; ++ } ++ ++#ifndef CROSS_DEBUGGER ++ ret = ptrace (PT_SETREGS, PIDGET (inferior_ptid), ++ (PTRACE_ARG3_TYPE) &inferior_registers, 0); ++ ++ if (ret < 0) ++ warning ("unable to store general registers"); ++#endif ++} ++ ++static void ++store_fp_register (int regno) ++{ ++ struct fpreg inferior_fp_registers; ++#ifndef CROSS_DEBUGGER ++ int ret; ++ ++ ret = ptrace (PT_GETFPREGS, PIDGET (inferior_ptid), ++ (PTRACE_ARG3_TYPE) &inferior_fp_registers, 0); ++ ++ if (ret < 0) ++ { ++ warning ("unable to fetch floating-point registers"); ++ return; ++ } ++#endif ++ ++ switch (regno) ++ { ++ case ARM_FPS_REGNUM: ++ regcache_collect (ARM_FPS_REGNUM, ++ (char *) &inferior_fp_registers.fpr_fpsr); ++ break; ++ ++ default: ++ regcache_collect ++ (regno, (char *) &inferior_fp_registers.fpr[regno - ARM_F0_REGNUM]); ++ break; ++ } ++ ++#ifndef CROSS_DEBUGGER ++ ret = ptrace (PT_SETFPREGS, PIDGET (inferior_ptid), ++ (PTRACE_ARG3_TYPE) &inferior_fp_registers, 0); ++ ++ if (ret < 0) ++ warning ("unable to write register %d to inferior", regno); ++#endif ++} ++ ++static void ++store_fp_regs (void) ++{ ++ struct fpreg inferior_fp_registers; ++ int ret; ++ int regno; ++ ++ ++ for (regno = ARM_F0_REGNUM; regno <= ARM_F7_REGNUM; regno++) ++ regcache_collect ++ (regno, (char *) &inferior_fp_registers.fpr[regno - ARM_F0_REGNUM]); ++ ++ regcache_collect (ARM_FPS_REGNUM, (char *) &inferior_fp_registers.fpr_fpsr); ++ ++#ifndef CROSS_DEBUGGER ++ ret = ptrace (PT_SETFPREGS, PIDGET (inferior_ptid), ++ (PTRACE_ARG3_TYPE) &inferior_fp_registers, 0); ++ ++ if (ret < 0) ++ warning ("unable to store floating-point registers"); ++#endif ++} ++ ++void ++store_inferior_registers (int regno) ++{ ++ if (regno >= 0) ++ { ++ if (regno < ARM_F0_REGNUM || regno > ARM_FPS_REGNUM) ++ store_register (regno); ++ else ++ store_fp_register (regno); ++ } ++ else ++ { ++ store_regs (); ++ store_fp_regs (); ++ } ++} ++ ++ ++struct md_core ++{ ++ struct reg intreg; ++ struct fpreg freg; ++}; ++ ++static void ++fetch_core_registers (char *core_reg_sect, unsigned core_reg_size, ++ int which, CORE_ADDR ignore) ++{ ++ struct md_core *core_reg = (struct md_core *) core_reg_sect; ++ int regno; ++ CORE_ADDR r_pc; ++ ++ supply_gregset (&core_reg->intreg); ++ supply_fpregset (&core_reg->freg); ++} ++ ++static void ++fetch_elfcore_registers (char *core_reg_sect, unsigned core_reg_size, ++ int which, CORE_ADDR ignore) ++{ ++ struct reg gregset; ++ struct fpreg fparegset; ++ ++ switch (which) >>> TRUNCATED FOR MAIL (1000 lines) <<<
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