From owner-svn-src-all@freebsd.org Tue Dec 15 13:17:41 2015 Return-Path: Delivered-To: svn-src-all@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id ACB6FA446FD; Tue, 15 Dec 2015 13:17:41 +0000 (UTC) (envelope-from skra@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 79C531EA0; Tue, 15 Dec 2015 13:17:41 +0000 (UTC) (envelope-from skra@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id tBFDHeCp037948; Tue, 15 Dec 2015 13:17:40 GMT (envelope-from skra@FreeBSD.org) Received: (from skra@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id tBFDHeHJ037947; Tue, 15 Dec 2015 13:17:40 GMT (envelope-from skra@FreeBSD.org) Message-Id: <201512151317.tBFDHeHJ037947@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: skra set sender to skra@FreeBSD.org using -f From: Svatopluk Kraus Date: Tue, 15 Dec 2015 13:17:40 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r292264 - head/sys/arm/arm X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 15 Dec 2015 13:17:41 -0000 Author: skra Date: Tue Dec 15 13:17:40 2015 New Revision: 292264 URL: https://svnweb.freebsd.org/changeset/base/292264 Log: Flush intermediate TLB cache when L2 page table is unlinked. This fixes an issue observed on Cortex A7 (RPi2) and on Cortex A15 (Jetson TK1) causing various memory corruptions. It turned out that even L2 page table with no valid mapping might be a subject of such caching. Note that not all platforms have intermediate TLB caching implemented. An open question is if this fix is sufficient for all platforms with this feature. Approved by: kib (mentor) Modified: head/sys/arm/arm/pmap-v6-new.c Modified: head/sys/arm/arm/pmap-v6-new.c ============================================================================== --- head/sys/arm/arm/pmap-v6-new.c Tue Dec 15 13:04:44 2015 (r292263) +++ head/sys/arm/arm/pmap-v6-new.c Tue Dec 15 13:17:40 2015 (r292264) @@ -2508,8 +2508,13 @@ pmap_unwire_pt2pg(pmap_t pmap, vm_offset KASSERT(m->md.pt2_wirecount[i] == 0, ("%s: pmap %p PT2 %u (PG %p) wired", __func__, pmap, i, m)); opte1 = pte1_load(pte1p); - if (pte1_is_link(opte1)) + if (pte1_is_link(opte1)) { pte1_clear(pte1p); + /* + * Flush intermediate TLB cache. + */ + pmap_tlb_flush(pmap, (m->pindex + i) << PTE1_SHIFT); + } #ifdef INVARIANTS else KASSERT((opte1 == 0) || pte1_is_section(opte1),