From owner-freebsd-current@FreeBSD.ORG Mon Nov 29 16:46:21 2010 Return-Path: Delivered-To: freebsd-current@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 003FD106564A; Mon, 29 Nov 2010 16:46:20 +0000 (UTC) (envelope-from alc@rice.edu) Received: from mh7.mail.rice.edu (mh7.mail.rice.edu [128.42.199.46]) by mx1.freebsd.org (Postfix) with ESMTP id BC14A8FC15; Mon, 29 Nov 2010 16:46:20 +0000 (UTC) Received: from mh7.mail.rice.edu (localhost.localdomain [127.0.0.1]) by mh7.mail.rice.edu (Postfix) with ESMTP id CD84128F7ED; Mon, 29 Nov 2010 10:46:19 -0600 (CST) X-Virus-Scanned: by amavis-2.6.4 at mh7.mail.rice.edu, auth channel Received: from mh7.mail.rice.edu ([127.0.0.1]) by mh7.mail.rice.edu (mh7.mail.rice.edu [127.0.0.1]) (amavis, port 10026) with ESMTP id 7fJfTa83WuVm; Mon, 29 Nov 2010 10:46:19 -0600 (CST) Received: from adsl-216-63-78-18.dsl.hstntx.swbell.net (adsl-216-63-78-18.dsl.hstntx.swbell.net [216.63.78.18]) (using TLSv1 with cipher RC4-MD5 (128/128 bits)) (No client certificate requested) (Authenticated sender: alc) by mh7.mail.rice.edu (Postfix) with ESMTPSA id 406E728F7D4; Mon, 29 Nov 2010 10:46:19 -0600 (CST) Message-ID: <4CF3D8DA.4050308@rice.edu> Date: Mon, 29 Nov 2010 10:46:18 -0600 From: Alan Cox User-Agent: Thunderbird 2.0.0.24 (X11/20100725) MIME-Version: 1.0 To: John Baldwin References: <1290387926.16558.1283.camel@home-yahoo> <201011221447.13026.jhb@freebsd.org> <4CEB126E.2010509@rice.edu> <201011290945.35128.jhb@freebsd.org> In-Reply-To: <201011290945.35128.jhb@freebsd.org> Content-Type: text/plain; charset=ISO-8859-15; format=flowed Content-Transfer-Encoding: 7bit X-Mailman-Approved-At: Mon, 29 Nov 2010 16:49:49 +0000 Cc: alc@freebsd.org, freebsd-current@freebsd.org, Sean Bruno Subject: Re: 40 vs 44 bit memory addressing HP DL580/980 X-BeenThere: freebsd-current@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Discussions about the use of FreeBSD-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 29 Nov 2010 16:46:21 -0000 John Baldwin wrote: > On Monday, November 22, 2010 8:01:34 pm Alan Cox wrote: > >> On 11/22/2010 1:47 PM, John Baldwin wrote: >> >>> On Monday, November 22, 2010 1:37:45 pm Alan Cox wrote: >>> >>>> On Mon, Nov 22, 2010 at 6:59 AM, John Baldwin wrote: >>>> >>>> >>>>> On Sunday, November 21, 2010 8:05:26 pm Sean Bruno wrote: >>>>> >>>>>> Looks like these HP boxes have the capability to do 44 bit memory >>>>>> addressing if configured to do so from the BIOS. >>>>>> >>>>>> Is anyone interested in any data from that setting? >>>>>> >>>>> Does it boot ok? :) The MTRR code should handle that (there is a CPUID >>>>> field that tells the OS how many bits are significant). Not sure if there >>>>> are any places in the pmap that assume 40 bits, but a test boot is >>>>> certainly >>>>> worth trying. >>>>> >>>>> >>>>> >>>> Since we don't boot with 40-bit addressing, I can easily predict the >>>> outcome. :-) >>>> >>>> The trouble with this machine is that the second 128GB of RAM is being >>>> placed between 512G and 1T in the physical address space, which is beyond >>>> the range of the (current) direct map. So, we take a page fault on the >>>> first access to a page in the second 128GB through the direct map. >>>> >>> Heh, I guess that is what your earlier patch did? Once that patch is applied >>> I think Sean should just try 44-bit mode if so. >>> >>> >> Yes. >> >> If 44-bit addressing makes the placement of DRAM in the physical address >> space any sparser, then we'll again have an insufficiently large direct >> map. Also, I fear that we won't be able to allocate the vm_page_array >> without enabling VM_PHYSSEG_SPARSE, which itself requires a change in >> order to work. >> > > I believe someone has a change for that on amd64 already? > > Yes. Alan