From owner-freebsd-arch@FreeBSD.ORG Tue Jan 16 23:06:25 2007 Return-Path: X-Original-To: freebsd-arch@freebsd.org Delivered-To: freebsd-arch@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [69.147.83.52]) by hub.freebsd.org (Postfix) with ESMTP id 6043616A47E; Tue, 16 Jan 2007 23:06:25 +0000 (UTC) (envelope-from jhb@freebsd.org) Received: from server.baldwin.cx (66-23-211-162.clients.speedfactory.net [66.23.211.162]) by mx1.freebsd.org (Postfix) with ESMTP id 0C0AB13C44B; Tue, 16 Jan 2007 23:06:24 +0000 (UTC) (envelope-from jhb@freebsd.org) Received: from localhost.corp.yahoo.com (john@localhost [127.0.0.1]) (authenticated bits=0) by server.baldwin.cx (8.13.6/8.13.6) with ESMTP id l0GN6Ca1047863; Tue, 16 Jan 2007 18:06:12 -0500 (EST) (envelope-from jhb@freebsd.org) From: John Baldwin To: freebsd-arch@freebsd.org Date: Tue, 16 Jan 2007 18:06:26 -0500 User-Agent: KMail/1.9.1 References: <3bbf2fe10607250813w8ff9e34pc505bf290e71758@mail.gmail.com> <3bbf2fe10701161454m74bd9356i3999187515c60596@mail.gmail.com> In-Reply-To: <3bbf2fe10701161454m74bd9356i3999187515c60596@mail.gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200701161806.27245.jhb@freebsd.org> X-Greylist: Sender succeeded SMTP AUTH authentication, not delayed by milter-greylist-2.0.2 (server.baldwin.cx [127.0.0.1]); Tue, 16 Jan 2007 18:06:13 -0500 (EST) X-Virus-Scanned: ClamAV 0.88.3/2457/Tue Jan 16 06:53:04 2007 on server.baldwin.cx X-Virus-Status: Clean X-Spam-Status: No, score=-4.4 required=4.2 tests=ALL_TRUSTED,AWL,BAYES_00 autolearn=ham version=3.1.3 X-Spam-Checker-Version: SpamAssassin 3.1.3 (2006-06-01) on server.baldwin.cx Cc: Attilio Rao , Ivan Voras Subject: Re: [PATCH] Mantaining turnstile aligned to 128 bytes in i386 CPUs X-BeenThere: freebsd-arch@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Discussion related to FreeBSD architecture List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 16 Jan 2007 23:06:25 -0000 On Tuesday 16 January 2007 17:54, Attilio Rao wrote: > 2007/1/16, Ivan Voras : > > Kip Macy wrote: > > > x86 pre-P4 had 32-byte cache lines. Thus older processors will not benefit. > > > > But it does seem to hurt the performance a bit - maybe it's time to add > > another CPU option like I586_CPU and I686_CPU? > > Well, it is my feeling that probabilly the align_cache parameter > should be a run-time settled parameter (in particular for ia32 CPUs > which changed a lot along the years). Yes. I think UMA_ALIGN_CACHE should be a magic cookie value and that the MD code should provide a cache line size to uma(4) during bootup, and I think you can probably just axe UMA_ALIGN_SYNC and use UMA_ALIGN_CACHE for the turnstile and sleep queue zones. -- John Baldwin