From owner-freebsd-hackers Fri Apr 11 23:04:21 1997 Return-Path: Received: (from root@localhost) by freefall.freebsd.org (8.8.5/8.8.5) id XAA16331 for hackers-outgoing; Fri, 11 Apr 1997 23:04:21 -0700 (PDT) Received: from becker1.u.washington.edu (spaz@becker1.u.washington.edu [140.142.12.67]) by freefall.freebsd.org (8.8.5/8.8.5) with ESMTP id XAA16326 for ; Fri, 11 Apr 1997 23:04:18 -0700 (PDT) Received: from localhost (spaz@localhost) by becker1.u.washington.edu (8.8.4+UW96.12/8.8.4+UW97.03) with SMTP id XAA01523; Fri, 11 Apr 1997 23:04:11 -0700 (PDT) Date: Fri, 11 Apr 1997 23:04:10 -0700 (PDT) From: John Utz To: Michael Smith cc: hackers@FreeBSD.org Subject: sorry bout the 'discredited architecture remark'Re: 430TX ? In-Reply-To: <199704120440.OAA29855@genesis.atrad.adelaide.edu.au> Message-ID: MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Sender: owner-hackers@FreeBSD.org X-Loop: FreeBSD.org Precedence: bulk Hi Michael; This is the second call i have received on my snide reference to harvard architecture as a 'discredited architecture'. It was an overly biased comment. i just think that separate instruction and data memory is a mistake because u wind up with too much of one and not enuf of the other too often. nonetheless, it obviously works, so i will slink off now..... On Sat, 12 Apr 1997, Michael Smith wrote: > John Utz stands accused of saying: > > > > > > While we're talking about Intel, they claim that they're focusing more on > > > memory bandwidth these days and the Pentium II has some kind of dual bus > > > architecture that makes a significant performance difference. > > > > my instructor claims they separated the cache into instruction > > cache and data-cache.....a previously 'discredited' architecture known to > > the ancients as 'harvard architecture ( howard aiken )' as opposed to the > > traditional 'von neumann' or 'princeton' architecture.... is cache space > > relatively cheap these days? > > Split I&D cache is nothing 'discredited' (cf. Sparc, Mips, Motorola), > and full-Havard CPUs have been around all along too (all of the m68k > family, for example). > > Cache space has nothing to do with it; the basic idea is that code and > data are not normally tightly mixed (instruction operands count as > 'code') and thus having seperate caches for them can be a Good Thing. > > It Intel are hailing this as some sort of 'breakthrough', then that's > just one more reason to laugh loudly at them. > > > John Utz spaz@u.washington.edu > > -- > ]] Mike Smith, Software Engineer msmith@gsoft.com.au [[ > ]] Genesis Software genesis@gsoft.com.au [[ > ]] High-speed data acquisition and (GSM mobile) 0411-222-496 [[ > ]] realtime instrument control. (ph) +61-8-8267-3493 [[ > ]] Unix hardware collector. "Where are your PEZ?" The Tick [[ > ******************************************************************************* John Utz spaz@u.washington.edu idiocy is the impulse function in the convolution of life