Date: Wed, 26 Aug 2020 02:04:04 +0000 (UTC) From: D Scott Phillips <scottph@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r364794 - head/sys/arm64/arm64 Message-ID: <202008260204.07Q244dt027525@repo.freebsd.org>
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Author: scottph Date: Wed Aug 26 02:04:04 2020 New Revision: 364794 URL: https://svnweb.freebsd.org/changeset/base/364794 Log: arm64: Make local stores observable before sending IPIs Add a synchronizing instruction to flush and wait until the local CPU's writes are observable to other CPUs before sending IPIs. This fixes an issue where recipient CPUs doing a rendezvous could enter the rendezvous handling code before the initiator's writes to the smp_rv_* variables were visible. This manifested as a system hang, where a single CPU's increment of smp_rv_waiters[0] actually happened "before" the initiator's zeroing of that field, so all CPUs were stuck with the field appearing to be at ncpus - 1. Reviewed by: andrew, markj Approved by: scottl (implicit) MFC after: 1 week Sponsored by: Ampere Computing, Inc. Differential Revision: https://reviews.freebsd.org/D25798 Modified: head/sys/arm64/arm64/mp_machdep.c Modified: head/sys/arm64/arm64/mp_machdep.c ============================================================================== --- head/sys/arm64/arm64/mp_machdep.c Wed Aug 26 01:55:37 2020 (r364793) +++ head/sys/arm64/arm64/mp_machdep.c Wed Aug 26 02:04:04 2020 (r364794) @@ -304,6 +304,13 @@ pic_ipi_send(void *arg, cpuset_t cpus, u_int ipi) { KASSERT(intr_irq_root_dev != NULL, ("%s: no root attached", __func__)); + + /* + * Ensure that this CPU's stores will be visible to IPI + * recipients before starting to send the interrupts. + */ + dsb(ishst); + PIC_IPI_SEND(intr_irq_root_dev, arg, cpus, ipi); }
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