From owner-svn-src-all@freebsd.org Sun Dec 18 08:31:03 2016 Return-Path: Delivered-To: svn-src-all@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 42ACAC86A6F; Sun, 18 Dec 2016 08:31:03 +0000 (UTC) (envelope-from jchandra@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id F09BB18BE; Sun, 18 Dec 2016 08:31:02 +0000 (UTC) (envelope-from jchandra@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id uBI8V2XZ059889; Sun, 18 Dec 2016 08:31:02 GMT (envelope-from jchandra@FreeBSD.org) Received: (from jchandra@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id uBI8V1VZ059886; Sun, 18 Dec 2016 08:31:01 GMT (envelope-from jchandra@FreeBSD.org) Message-Id: <201612180831.uBI8V1VZ059886@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: jchandra set sender to jchandra@FreeBSD.org using -f From: "Jayachandran C." Date: Sun, 18 Dec 2016 08:31:01 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r310204 - in head/sys: arm/arm arm64/arm64 X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 18 Dec 2016 08:31:03 -0000 Author: jchandra Date: Sun Dec 18 08:31:01 2016 New Revision: 310204 URL: https://svnweb.freebsd.org/changeset/base/310204 Log: Initialize GIC[DR]_IGROUPRn registers for GICv3 In case where GICD_CTLR.DS is 1, the IGROUPR registers are RW in non-secure state and has to be initialized to 1 for the corresponding interrupts to be delivered as Group 1 interrupts. Update gic_v3_dist_init() and gic_v3_redist_init() to initialize GICD_IGROUPRn and GICR_IGROUPRn respectively to address this. The registers can be set unconditionally since the writes are ignored in non-secure state when GICD_CTLR.DS is 0. This fixes the hang on boot seen when running qemu-system-aarch64 with machine virt,gic-version=3 Modified: head/sys/arm/arm/gic_common.h head/sys/arm64/arm64/gic_v3.c head/sys/arm64/arm64/gic_v3_reg.h Modified: head/sys/arm/arm/gic_common.h ============================================================================== --- head/sys/arm/arm/gic_common.h Sun Dec 18 05:36:04 2016 (r310203) +++ head/sys/arm/arm/gic_common.h Sun Dec 18 08:31:01 2016 (r310204) @@ -66,6 +66,7 @@ __BUS_ACCESSOR(gic, bus, GIC, BUS, u_int #define GICD_IIDR_IMPL(x) \ (((x) & GICD_IIDR_IMPL_MASK) >> GICD_IIDR_IMPL_SHIFT) #define GICD_IGROUPR(n) (0x0080 + (((n) >> 5) * 4)) /* v1 ICDISER */ +#define GICD_I_PER_IGROUPRn 32 #define GICD_ISENABLER(n) (0x0100 + (((n) >> 5) * 4)) /* v1 ICDISER */ #define GICD_I_MASK(n) (1ul << ((n) & 0x1f)) #define GICD_I_PER_ISENABLERn 32 Modified: head/sys/arm64/arm64/gic_v3.c ============================================================================== --- head/sys/arm64/arm64/gic_v3.c Sun Dec 18 05:36:04 2016 (r310203) +++ head/sys/arm64/arm64/gic_v3.c Sun Dec 18 08:31:01 2016 (r310204) @@ -1040,6 +1040,10 @@ gic_v3_dist_init(struct gic_v3_softc *sc /* * 2. Configure the Distributor */ + /* Set all SPIs to be Group 1 Non-secure */ + for (i = GIC_FIRST_SPI; i < sc->gic_nirqs; i += GICD_I_PER_IGROUPRn) + gic_d_write(sc, 4, GICD_IGROUPR(i), 0xFFFFFFFF); + /* Set all global interrupts to be level triggered, active low. */ for (i = GIC_FIRST_SPI; i < sc->gic_nirqs; i += GICD_I_PER_ICFGRn) gic_d_write(sc, 4, GICD_ICFGR(i), 0x00000000); @@ -1206,6 +1210,10 @@ gic_v3_redist_init(struct gic_v3_softc * if (err != 0) return (err); + /* Configure SGIs and PPIs to be Group1 Non-secure */ + gic_r_write(sc, 4, GICR_SGI_BASE_SIZE + GICR_IGROUPR0, + 0xFFFFFFFF); + /* Disable SPIs */ gic_r_write(sc, 4, GICR_SGI_BASE_SIZE + GICR_ICENABLER0, GICR_I_ENABLER_PPI_MASK); Modified: head/sys/arm64/arm64/gic_v3_reg.h ============================================================================== --- head/sys/arm64/arm64/gic_v3_reg.h Sun Dec 18 05:36:04 2016 (r310203) +++ head/sys/arm64/arm64/gic_v3_reg.h Sun Dec 18 08:31:01 2016 (r310204) @@ -194,6 +194,7 @@ #define GICR_VLPI_BASE_SIZE PAGE_SIZE_64K #define GICR_RESERVED_SIZE PAGE_SIZE_64K +#define GICR_IGROUPR0 (0x0080) #define GICR_ISENABLER0 (0x0100) #define GICR_ICENABLER0 (0x0180) #define GICR_I_ENABLER_SGI_MASK (0x0000FFFF)