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Date:      Tue, 14 Feb 2012 00:20:10 GMT
From:      dfilter@FreeBSD.ORG (dfilter service)
To:        freebsd-scsi@FreeBSD.org
Subject:   Re: kern/163812: commit references a PR
Message-ID:  <201202140020.q1E0KAt8032909@freefall.freebsd.org>

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The following reply was made to PR kern/163812; it has been noted by GNATS.

From: dfilter@FreeBSD.ORG (dfilter service)
To: bug-followup@FreeBSD.org
Cc:  
Subject: Re: kern/163812: commit references a PR
Date: Tue, 14 Feb 2012 00:18:50 +0000 (UTC)

 Author: marius
 Date: Tue Feb 14 00:18:35 2012
 New Revision: 231621
 URL: http://svn.freebsd.org/changeset/base/231621
 
 Log:
   - As it turns out, MSI-X is broken for at least LSI SAS1068E when passed
     through by VMware so blacklist their PCI-PCI bridge for MSI/MSI-X here.
     Note that besides currently there not being a quirk type that disables
     MSI-X only and there's no evidence that MSI doesn't work with the VMware
     pass-through, it's really questionable whether MSI generally works in
     that setup as VMware only mention three know working devices [1, p. 4].
     Also not that this quirk entry currently doesn't affect the devices
     emulated by VMware in any way as these don't claim support MSI/MSI-X to
     begin with. [2]
     While at it, make the PCI quirk table const and static.
   - Remove some duplicated empty lines.
   - Use DEVMETHOD_END.
   
   PR:		163812, http://forums.freebsd.org/showthread.php?t=27899 [2]
   Reviewed by:	jhb
   MFC after:	3 days
 
 Modified:
   head/sys/dev/pci/pci.c
 
 Modified: head/sys/dev/pci/pci.c
 ==============================================================================
 --- head/sys/dev/pci/pci.c	Tue Feb 14 00:18:18 2012	(r231620)
 +++ head/sys/dev/pci/pci.c	Tue Feb 14 00:18:35 2012	(r231621)
 @@ -73,7 +73,6 @@ __FBSDID("$FreeBSD$");
  #define	PCIR_IS_BIOS(cfg, reg)						\
  	(((cfg)->hdrtype == PCIM_HDRTYPE_NORMAL && reg == PCIR_BIOS) ||	\
  	 ((cfg)->hdrtype == PCIM_HDRTYPE_BRIDGE && reg == PCIR_BIOS_1))
 -	    
  
  static pci_addr_t	pci_mapbase(uint64_t mapreg);
  static const char	*pci_maptype(uint64_t mapreg);
 @@ -171,7 +170,7 @@ static device_method_t pci_methods[] = {
  	DEVMETHOD(pci_msi_count,	pci_msi_count_method),
  	DEVMETHOD(pci_msix_count,	pci_msix_count_method),
  
 -	{ 0, 0 }
 +	DEVMETHOD_END
  };
  
  DEFINE_CLASS_0(pci, pci_driver, pci_methods, 0);
 @@ -183,7 +182,6 @@ MODULE_VERSION(pci, 1);
  static char	*pci_vendordata;
  static size_t	pci_vendordata_size;
  
 -
  struct pci_quirk {
  	uint32_t devid;	/* Vendor/device of the card */
  	int	type;
 @@ -194,7 +192,7 @@ struct pci_quirk {
  	int	arg2;
  };
  
 -struct pci_quirk pci_quirks[] = {
 +static const struct pci_quirk const pci_quirks[] = {
  	/* The Intel 82371AB and 82443MX has a map register at offset 0x90. */
  	{ 0x71138086, PCI_QUIRK_MAP_REG,	0x90,	 0 },
  	{ 0x719b8086, PCI_QUIRK_MAP_REG,	0x90,	 0 },
 @@ -227,6 +225,12 @@ struct pci_quirk pci_quirks[] = {
  	{ 0x74501022, PCI_QUIRK_DISABLE_MSI,	0,	0 },
  
  	/*
 +	 * MSI-X doesn't work with at least LSI SAS1068E passed through by
 +	 * VMware.
 +	 */
 +	{ 0x079015ad, PCI_QUIRK_DISABLE_MSI,	0,	0 },
 +
 +	/*
  	 * Some virtualization environments emulate an older chipset
  	 * but support MSI just fine.  QEMU uses the Intel 82440.
  	 */
 @@ -724,7 +728,6 @@ pci_read_cap(device_t pcib, pcicfgregs *
  		}
  	}
  
 -	
  #if defined(__i386__) || defined(__amd64__) || defined(__powerpc__)
  	/*
  	 * Enable the MSI mapping window for all HyperTransport
 @@ -1873,7 +1876,7 @@ pci_remap_intr_method(device_t bus, devi
  int
  pci_msi_device_blacklisted(device_t dev)
  {
 -	struct pci_quirk *q;
 +	const struct pci_quirk *q;
  
  	if (!pci_honor_msi_blacklist)
  		return (0);
 @@ -1893,7 +1896,7 @@ pci_msi_device_blacklisted(device_t dev)
  static int
  pci_msi_vm_chipset(device_t dev)
  {
 -	struct pci_quirk *q;
 +	const struct pci_quirk *q;
  
  	for (q = &pci_quirks[0]; q->devid; q++) {
  		if (q->devid == pci_get_devid(dev) &&
 @@ -3023,7 +3026,7 @@ pci_add_resources(device_t bus, device_t
  	struct pci_devinfo *dinfo = device_get_ivars(dev);
  	pcicfgregs *cfg = &dinfo->cfg;
  	struct resource_list *rl = &dinfo->resources;
 -	struct pci_quirk *q;
 +	const struct pci_quirk *q;
  	int i;
  
  	/* ATA devices needs special map treatment */
 @@ -3864,7 +3867,6 @@ pci_write_ivar(device_t dev, device_t ch
  	}
  }
  
 -
  #include "opt_ddb.h"
  #ifdef DDB
  #include <ddb/ddb.h>
 @@ -4021,7 +4023,6 @@ out:;
  	return (res);
  }
  
 -
  struct resource *
  pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
  		   u_long start, u_long end, u_long count, u_int flags)
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