From owner-freebsd-current@FreeBSD.ORG Fri Feb 3 23:58:38 2006 Return-Path: X-Original-To: freebsd-current@freebsd.org Delivered-To: freebsd-current@freebsd.org Received: from [127.0.0.1] (localhost [127.0.0.1]) by hub.freebsd.org (Postfix) with ESMTP id 93AF916A425; Fri, 3 Feb 2006 23:58:37 +0000 (GMT) (envelope-from davidxu@freebsd.org) Message-ID: <43E3EE2D.10001@freebsd.org> Date: Sat, 04 Feb 2006 07:58:37 +0800 From: David Xu User-Agent: Mozilla/5.0 (X11; U; FreeBSD amd64; en-US; rv:1.7.12) Gecko/20060117 X-Accept-Language: en-us, en MIME-Version: 1.0 To: Andrew Gallatin References: <17379.56708.421007.613310@grasshopper.cs.duke.edu> In-Reply-To: <17379.56708.421007.613310@grasshopper.cs.duke.edu> Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit Cc: freebsd-current@freebsd.org Subject: Re: machdep.cpu_idle_hlt and SMP perf? X-BeenThere: freebsd-current@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Discussions about the use of FreeBSD-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 03 Feb 2006 23:58:38 -0000 Andrew Gallatin wrote: >Why dooes machdep.cpu_idle_hlt=1 drop my 10GbE network rx >performance by a considerable amount (7.5Gbs -> 5.5Gbs)? > >I've (blindly) tried leaving machdep.cpu_idle_hlt=1 enabled >and playing with the vast array of kern.sched.ipiwakeup.* sysctls, >but receive performance remains limited to ~5.5Gb/sec or less. > >This is an 'AMD Athlon(tm) 64 X2 Dual Core Processor 3800+' running >FreeBSD-current as of about one week ago. The interrupt load is >about 22,000 device interrupts/sec (ithreaded). Interestingly, >the more I decrease the interrupt load by increasing the interrupt >coalescing timer, the worse the machdep.cpu_idle_hlt=1 case does. > >Is this just a case of the wakeup IPI taking a long time or blocking >on some lock? > >Drew > >PS: Here is what I mean: > > I am thinking if we can rewrite cpu idle code by using mwait instruction on pentium4, it should reduce latency, I don't know if Athlon 64 supports this instruction yet. David Xu