From owner-freebsd-arch@FreeBSD.ORG Wed Oct 24 21:27:31 2012 Return-Path: Delivered-To: freebsd-arch@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [69.147.83.52]) by hub.freebsd.org (Postfix) with ESMTP id ED45A2CA; Wed, 24 Oct 2012 21:27:31 +0000 (UTC) (envelope-from adrian.chadd@gmail.com) Received: from mail-pa0-f54.google.com (mail-pa0-f54.google.com [209.85.220.54]) by mx1.freebsd.org (Postfix) with ESMTP id B4C558FC08; Wed, 24 Oct 2012 21:27:31 +0000 (UTC) Received: by mail-pa0-f54.google.com with SMTP id bi1so703964pad.13 for ; Wed, 24 Oct 2012 14:27:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:sender:in-reply-to:references:date :x-google-sender-auth:message-id:subject:from:to:cc:content-type; bh=6h1eC2WLLc3huxWNqjJRk9dRBvc5FWFvIRtHa7CAdPk=; b=K94hBL7gahgKxTeWWVtHqacvig4D67cNJjGZbEUQLimDhRMaisINtZizI+/EY9g8xi tyaIcZoAYNBgCuLRTMQ2HaAzLPAfDTo7flkunA6V4J4IAj3FIQZ/pfCs2r7Y7h/OctKV a0dl73LrlnbirpHFHJoXF7J/VqGqBOteD2/lXppDt0xiY8hYcVc+KpCUDySRpErS+OfK V5rVPwCPWKQV2jhKvfy6cTGYM5eZAfNp/hjli0p7EKbN5fHGLXqe17IdjAGX2D8YXqWr XrlgPSP2yqjeHVxOsMcgN865cDH7zOuHjhv4Z1bPmVAJZL1yiRJfNJG9eOsY8Y8U8NNG be8w== MIME-Version: 1.0 Received: by 10.68.197.9 with SMTP id iq9mr52876439pbc.130.1351114051291; Wed, 24 Oct 2012 14:27:31 -0700 (PDT) Sender: adrian.chadd@gmail.com Received: by 10.68.146.233 with HTTP; Wed, 24 Oct 2012 14:27:31 -0700 (PDT) In-Reply-To: References: Date: Wed, 24 Oct 2012 14:27:31 -0700 X-Google-Sender-Auth: eS3fqXP1WQGWCsZ-55lPIdDtLq0 Message-ID: Subject: Re: CACHE_LINE_SIZE on x86 From: Adrian Chadd To: Jim Harris Content-Type: text/plain; charset=ISO-8859-1 Cc: freebsd-arch@freebsd.org X-BeenThere: freebsd-arch@freebsd.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: Discussion related to FreeBSD architecture List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 24 Oct 2012 21:27:32 -0000 On 24 October 2012 12:13, Jim Harris wrote: > While investigating padding of the ULE scheduler locks (r242014), I > recently discovered that CACHE_LINE_SIZE on x86 is defined as 128 (not > 64). From what I can tell from svn logs, this was to account for 128 > byte cache "sectors" that existed on the NetBurst micro architecture > CPUs. > > I'm curious if there's been consideration in changing this back to 64? > With maybe a kernel config option to modify it? On 2S systems (but > not on 1S systems), I see a benefit using CACHE_LINE_SIZE=128 for the > scheduler locks. I suspect this is related to data prefetching but am > still running experiments to verify. Well, is it worth maintaining multiple alignment options, for aligning different things? eg cache alignment for memory allocations, larger alignment for compile-time structure alignment, etc? Adrian