From owner-freebsd-arm@FreeBSD.ORG Tue Sep 10 16:13:40 2013 Return-Path: Delivered-To: freebsd-arm@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [8.8.178.115]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTP id 2A6D4947 for ; Tue, 10 Sep 2013 16:13:40 +0000 (UTC) (envelope-from imp@bsdimp.com) Received: from mail-qe0-f48.google.com (mail-qe0-f48.google.com [209.85.128.48]) (using TLSv1 with cipher ECDHE-RSA-RC4-SHA (128/128 bits)) (No client certificate requested) by mx1.freebsd.org (Postfix) with ESMTPS id DDB9F271D for ; Tue, 10 Sep 2013 16:13:39 +0000 (UTC) Received: by mail-qe0-f48.google.com with SMTP id nd7so3507021qeb.21 for ; Tue, 10 Sep 2013 09:13:33 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:sender:subject:mime-version:content-type:from :in-reply-to:date:cc:content-transfer-encoding:message-id:references :to; bh=9073uxqBVAqatJGv4xGdfIiV5mzhbvyM+AVfJr4Iqr8=; b=bF4QRyGlS2B/UZBIiv9R/qn/GauSF+1ZTOJwXseBZfxptz41kelcokd8nPaexXh4nB AO6ul3qLSa86y850HE+DEjVyfIW9pXEyeA9ZMLnVccWEJiJJ1NJPWE1/hkENzFpWLQqS w//kzVxQHqP9Uxl06IyNt8gdaBe8CxgR0QUWxNsRlShRIYUp5Rr5gpH+LeYorkJzLWy8 q0aCCNm8LhdfVKLd/MEzJJC4ARQ9DjnNpYm1I3LXq42UioRZApMud7gm6NR2uHxZIsYY dQzAo4iI0ZhclK2/sF525O1l2sv4BVAufA52h5lqraPLpypVCijGO8TUIZ4wbM5hiGYD nPHQ== X-Gm-Message-State: ALoCoQnvJRqpXElIlbJOBVWUNR0P9p4ZEGgNa5jRAAibw81pm15oCt84PJwtxoCJ8w4dmjcRjaf2 X-Received: by 10.49.49.74 with SMTP id s10mr33278695qen.29.1378829612952; Tue, 10 Sep 2013 09:13:32 -0700 (PDT) Received: from fusionlt2834a.int.fusionio.com ([209.117.142.2]) by mx.google.com with ESMTPSA id u8sm36072514qef.3.1969.12.31.16.00.00 (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 10 Sep 2013 09:13:32 -0700 (PDT) Sender: Warner Losh Subject: Re: Architecture vs. bus vs. device DMA cache coherency Mime-Version: 1.0 (Apple Message framework v1085) Content-Type: text/plain; charset=us-ascii From: Warner Losh In-Reply-To: <20130910154335.GT68682@funkthat.com> Date: Tue, 10 Sep 2013 10:13:31 -0600 Content-Transfer-Encoding: quoted-printable Message-Id: References: <20130910154335.GT68682@funkthat.com> To: John-Mark Gurney X-Mailer: Apple Mail (2.1085) Cc: freebsd-arm@freebsd.org X-BeenThere: freebsd-arm@freebsd.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: Porting FreeBSD to the StrongARM Processor List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 10 Sep 2013 16:13:40 -0000 On Sep 10, 2013, at 9:43 AM, John-Mark Gurney wrote: > Svatopluk Kraus wrote this message on Tue, Sep 10, 2013 at 13:19 = +0200: >> Even in DMA cache coherent architectures there could be not-coherent = DMA >> busses and/or devices. Thus, each bus and/or device should be = described by >> its bus_dma_tag and the tag should carry information about DMA cache >> coherency. >=20 > I've thought about this a lot myself, and I'm not familar w/ a bus = (that > isn't main memory) or device that isn't cache coherent... Most busses > write to memory through an arbiter (north bridge or cpu/soc) that does > the proper read/modify/write cycles to get the memory there. I have > not heard of another bus/device that does their own read/modify/write > cycles to get their writes to memory. Can you name a current = bus/device > that does this? >=20 > Our busdma system does have issues that if you try to dma to say, > video memory, we don't handle that (well) because we assume that all > memory is a flat space and belongs to nexus, but this isn't always > correct. >=20 > If you have an architecture like this, can you please tell use which > system you are trying to fix? I know that MIPS has different kinds of coherency as well that we = generally map to coherent (meaning coherent enough for the users) or = incoherent. Something to keep in mind. I generally like the idea, but don't have enough experience with kind of = hardware to know if the design is a good one. Warner