From nobody Wed Mar 25 04:46:54 2026 X-Original-To: dev-commits-src-all@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id 4fgZBW6S7Kz6WhqT for ; Wed, 25 Mar 2026 04:46:59 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "R12" (not verified)) by mx1.freebsd.org (Postfix) with ESMTPS id 4fgZBW3Zzqz3mSY for ; Wed, 25 Mar 2026 04:46:59 +0000 (UTC) (envelope-from git@FreeBSD.org) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1774414019; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=3Ru1U4ZRA72SGVN/XP7ci55eHIO2WCDDj9RtsI78LAc=; b=PMH3jDLt+6idM/eHVBV+c1aPjQaIZvxDep/YGT0FCyVQ0DAIXjTHdi4yXg8LcTZqzuM6tv k9/zcYgRuODzRvQx7vOh+muezrhXh2kSYvIeXwRErrRNyBYmf3c0FBhl4q1Y+LD2aC04O/ RuWHpLeq+vxFI4GDwBli3xs0wB2fN/IcMV9sRl43ZMhTR+brn16AsHSaHq/eEEcS2alCA+ Wo4ts9redrbvEutHsRD1GxFSyqNsxBTDqKvZEsL/CoC2v5CdRN54Iu2QYxTmKzRCfn5n+7 M+39pjgsP6aaVrXcoINiWtvFoiVz/e+TR2EZFMJPJFHJUFMydxLM0LfD2uXgww== ARC-Seal: i=1; s=dkim; d=freebsd.org; t=1774414019; a=rsa-sha256; cv=none; b=llVF7qIeAqsz7EKkhzpp3fh18dj5SQ8Df00H6sYhspkLYwvnJI8T3kgX6L1hQghIwb+8P2 oXwQWmb7H0IW7PjQSAy//oveuTIy2/uj5pN2Gi/q1DBy5gwUhomQNq7R9VJWlJtt85vEH7 lJJJNfTTNOx8uiBWcB/L5xcfwzNQ3+UXGtnSje7m84cyBBnb2u3C3VQYeTRrFSklteEAQy v/FuH4TlUh/0XkDzWsVIO4QGYQYG0nSlqeZIm2YbEYcwUmsMmevzxE2XCZ4tDl6lc5wwGN /LmhCdAvy7XkynrzWOpEqUi2gTgfz5+n1dx3LcPMlIm8KbeEU6tbSgH73Ri+kg== ARC-Authentication-Results: i=1; mx1.freebsd.org; none ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1774414019; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=3Ru1U4ZRA72SGVN/XP7ci55eHIO2WCDDj9RtsI78LAc=; b=Z0iup7tngHJjm2cuzlu47x3AYOXzl1vuBp+E7rX8rs/wyXiDoCqT3t0FordHY+miM43tZ8 BvEpILYM4nMftcUEt3En/FXbr52U4xDZOK8awXkRgJMRnQovYgjM7Vm9vwqcPt9SDzs6SI EjK6wR2zFSHmogk5kgzFs6u0IdY0USZl492TIMTpAviosP3e5jy1rsq9m7jiLnZL+qs/m0 sgR0FHmqmzY3ODH1vlK9FQtWxVjx8t2ku75ty15zUtBMUpEMHnbOW6beZV6fymXU/XTnF0 7PrG85e4c2QmEkh7fbwD60xhj+JH2BvmBy9mk5ysldBSVAp8fK12x1PxATCvnw== Received: from gitrepo.freebsd.org (gitrepo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:5]) by mxrelay.nyi.freebsd.org (Postfix) with ESMTP id 4fgZBW1yZYzqjc for ; Wed, 25 Mar 2026 04:46:59 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from git (uid 1279) (envelope-from git@FreeBSD.org) id 36bbe by gitrepo.freebsd.org (DragonFly Mail Agent v0.13+ on gitrepo.freebsd.org); Wed, 25 Mar 2026 04:46:54 +0000 To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-main@FreeBSD.org From: Jaeyoon Choi Subject: git: c4386988baa2 - main - ufshci: fix bug in ufshci_req_sdb_enable List-Id: Commit messages for all branches of the src repository List-Archive: https://lists.freebsd.org/archives/dev-commits-src-all List-Help: List-Post: List-Subscribe: List-Unsubscribe: X-BeenThere: dev-commits-src-all@freebsd.org Sender: owner-dev-commits-src-all@FreeBSD.org MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Git-Committer: jaeyoon X-Git-Repository: src X-Git-Refname: refs/heads/main X-Git-Reftype: branch X-Git-Commit: c4386988baa2ecdcb482c8ccace183dc643d097c Auto-Submitted: auto-generated Date: Wed, 25 Mar 2026 04:46:54 +0000 Message-Id: <69c368be.36bbe.6582e4ba@gitrepo.freebsd.org> The branch main has been updated by jaeyoon: URL: https://cgit.FreeBSD.org/src/commit/?id=c4386988baa2ecdcb482c8ccace183dc643d097c commit c4386988baa2ecdcb482c8ccace183dc643d097c Author: Jaeyoon Choi AuthorDate: 2026-03-24 05:12:14 +0000 Commit: Jaeyoon Choi CommitDate: 2026-03-24 16:45:27 +0000 ufshci: fix bug in ufshci_req_sdb_enable When enabling the request queue, safely reset the list base address. This was added due to a quirk in the Qualcomm UFS controller during the process of activating it. Sponsored by: Samsung Electronics Reviewed by: imp (mentor) Differential Revision: https://reviews.freebsd.org/D55984 --- sys/dev/ufshci/ufshci_req_sdb.c | 40 ++++++++++++++++++++++++++++++++++++---- 1 file changed, 36 insertions(+), 4 deletions(-) diff --git a/sys/dev/ufshci/ufshci_req_sdb.c b/sys/dev/ufshci/ufshci_req_sdb.c index ca47aa159c5b..54542f48b32c 100644 --- a/sys/dev/ufshci/ufshci_req_sdb.c +++ b/sys/dev/ufshci/ufshci_req_sdb.c @@ -374,34 +374,63 @@ ufshci_req_sdb_enable(struct ufshci_controller *ctrlr, struct ufshci_req_queue *req_queue) { struct ufshci_hw_queue *hwq = &req_queue->hwq[UFSHCI_SDB_Q]; + int error = 0; + + mtx_lock(&hwq->recovery_lock); + mtx_lock(&hwq->qlock); if (req_queue->is_task_mgmt) { uint32_t hcs, utmrldbr, utmrlrsr; + uint32_t utmrlba, utmrlbau; + + /* + * Some controllers require re-enabling. When a controller is + * re-enabled, the utmrlba registers are initialized, and these + * must be reconfigured upon re-enabling. + */ + utmrlba = hwq->req_queue_addr & 0xffffffff; + utmrlbau = hwq->req_queue_addr >> 32; + ufshci_mmio_write_4(ctrlr, utmrlba, utmrlba); + ufshci_mmio_write_4(ctrlr, utmrlbau, utmrlbau); hcs = ufshci_mmio_read_4(ctrlr, hcs); if (!(hcs & UFSHCIM(UFSHCI_HCS_REG_UTMRLRDY))) { ufshci_printf(ctrlr, "UTP task management request list is not ready\n"); - return (ENXIO); + error = ENXIO; + goto out; } utmrldbr = ufshci_mmio_read_4(ctrlr, utmrldbr); if (utmrldbr != 0) { ufshci_printf(ctrlr, "UTP task management request list door bell is not ready\n"); - return (ENXIO); + error = ENXIO; + goto out; } utmrlrsr = UFSHCIM(UFSHCI_UTMRLRSR_REG_UTMRLRSR); ufshci_mmio_write_4(ctrlr, utmrlrsr, utmrlrsr); } else { uint32_t hcs, utrldbr, utrlcnr, utrlrsr; + uint32_t utrlba, utrlbau; + + /* + * Some controllers require re-enabling. When a controller is + * re-enabled, the utrlba registers are initialized, and these + * must be reconfigured upon re-enabling. + */ + utrlba = hwq->req_queue_addr & 0xffffffff; + utrlbau = hwq->req_queue_addr >> 32; + ufshci_mmio_write_4(ctrlr, utrlba, utrlba); + ufshci_mmio_write_4(ctrlr, utrlbau, utrlbau); hcs = ufshci_mmio_read_4(ctrlr, hcs); if (!(hcs & UFSHCIM(UFSHCI_HCS_REG_UTRLRDY))) { ufshci_printf(ctrlr, "UTP transfer request list is not ready\n"); - return (ENXIO); + error = ENXIO; + goto out; } utrldbr = ufshci_mmio_read_4(ctrlr, utrldbr); @@ -434,7 +463,10 @@ ufshci_req_sdb_enable(struct ufshci_controller *ctrlr, hwq->recovery_state = RECOVERY_NONE; - return (0); +out: + mtx_unlock(&hwq->qlock); + mtx_unlock(&hwq->recovery_lock); + return (error); } int