From owner-freebsd-mips@FreeBSD.ORG Tue Jun 22 06:42:20 2010 Return-Path: Delivered-To: freebsd-mips@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 36365106566B; Tue, 22 Jun 2010 06:42:20 +0000 (UTC) (envelope-from imp@bsdimp.com) Received: from harmony.bsdimp.com (bsdimp.com [199.45.160.85]) by mx1.freebsd.org (Postfix) with ESMTP id EA7FE8FC12; Tue, 22 Jun 2010 06:42:19 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) by harmony.bsdimp.com (8.14.3/8.14.1) with ESMTP id o5M6efGs042437; Tue, 22 Jun 2010 00:40:41 -0600 (MDT) (envelope-from imp@bsdimp.com) Date: Tue, 22 Jun 2010 00:40:48 -0600 (MDT) Message-Id: <20100622.004048.624519315654756672.imp@bsdimp.com> To: c.jayachandran@gmail.com From: "M. Warner Losh" In-Reply-To: References: <20100621.164056.10150326092187581.imp@bsdimp.com> X-Mailer: Mew version 6.3 on Emacs 22.3 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=iso-8859-1 Content-Transfer-Encoding: quoted-printable Cc: freebsd-mips@freebsd.org Subject: Re: Merging 64 bit changes to -HEAD - part 3 X-BeenThere: freebsd-mips@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Porting FreeBSD to MIPS List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 22 Jun 2010 06:42:20 -0000 In message: "Jayachandran C." writes: : On Tue, Jun 22, 2010 at 4:10 AM, M. Warner Losh wrot= e: : > The changes to asm.h change the ABI for all ABIs, no? =A0Does that : > matter? =A0The jumpbuf is a user-visible thing... =A0I'm guessing t= hat we : > can say it is OK, but it sure would be nice if we could MFC this : > change before 8.1-RELEASE (but given the locked-down nature of the : > tree, I'm not hopeful). : = : Currently, it should not disturb the o32 ABI, since it is inside an i= fdef. : In n32/n64 the jmpbuf entries are 64bit and we will use one more : register for GP. Good point. I missed that when I was looking at it. My bad.a : Slightly off-topic, _JBLEN is 95 for mips, I cannot see a reason for= : this value, any hints? Hmmm. 31 normal registers (we don't save $0 :). 32 floating point registers that are double size. 31 + 2 * 32 =3D=3D 95. Maybe that's why... There's at least one Mips that has CP1 registers for its specialized hardware. If we ever are going to support saving/restoring that state along with the core and FP registers, we will need to expand this... Warner