From owner-svn-src-head@freebsd.org Fri Apr 14 08:11:51 2017 Return-Path: Delivered-To: svn-src-head@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 58A9DD3C2BE; Fri, 14 Apr 2017 08:11:51 +0000 (UTC) (envelope-from yongari@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 2D3AF149E; Fri, 14 Apr 2017 08:11:51 +0000 (UTC) (envelope-from yongari@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id v3E8BoPW011806; Fri, 14 Apr 2017 08:11:50 GMT (envelope-from yongari@FreeBSD.org) Received: (from yongari@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id v3E8BoSa011805; Fri, 14 Apr 2017 08:11:50 GMT (envelope-from yongari@FreeBSD.org) Message-Id: <201704140811.v3E8BoSa011805@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: yongari set sender to yongari@FreeBSD.org using -f From: Pyun YongHyeon Date: Fri, 14 Apr 2017 08:11:50 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r316820 - head/sys/dev/jme X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 14 Apr 2017 08:11:51 -0000 Author: yongari Date: Fri Apr 14 08:11:50 2017 New Revision: 316820 URL: https://svnweb.freebsd.org/changeset/base/316820 Log: Don't overwrite mapped bits. Found by: PVS-Studio Modified: head/sys/dev/jme/if_jme.c Modified: head/sys/dev/jme/if_jme.c ============================================================================== --- head/sys/dev/jme/if_jme.c Fri Apr 14 07:27:23 2017 (r316819) +++ head/sys/dev/jme/if_jme.c Fri Apr 14 08:11:50 2017 (r316820) @@ -557,7 +557,7 @@ jme_map_intr_vector(struct jme_softc *sc bzero(map, sizeof(map)); /* Map Tx interrupts source to MSI/MSIX vector 2. */ - map[MSINUM_REG_INDEX(N_INTR_TXQ0_COMP)] = + map[MSINUM_REG_INDEX(N_INTR_TXQ0_COMP)] |= MSINUM_INTR_SOURCE(2, N_INTR_TXQ0_COMP); map[MSINUM_REG_INDEX(N_INTR_TXQ1_COMP)] |= MSINUM_INTR_SOURCE(2, N_INTR_TXQ1_COMP); @@ -579,37 +579,37 @@ jme_map_intr_vector(struct jme_softc *sc MSINUM_INTR_SOURCE(2, N_INTR_TXQ_COAL_TO); /* Map Rx interrupts source to MSI/MSIX vector 1. */ - map[MSINUM_REG_INDEX(N_INTR_RXQ0_COMP)] = + map[MSINUM_REG_INDEX(N_INTR_RXQ0_COMP)] |= MSINUM_INTR_SOURCE(1, N_INTR_RXQ0_COMP); - map[MSINUM_REG_INDEX(N_INTR_RXQ1_COMP)] = + map[MSINUM_REG_INDEX(N_INTR_RXQ1_COMP)] |= MSINUM_INTR_SOURCE(1, N_INTR_RXQ1_COMP); - map[MSINUM_REG_INDEX(N_INTR_RXQ2_COMP)] = + map[MSINUM_REG_INDEX(N_INTR_RXQ2_COMP)] |= MSINUM_INTR_SOURCE(1, N_INTR_RXQ2_COMP); - map[MSINUM_REG_INDEX(N_INTR_RXQ3_COMP)] = + map[MSINUM_REG_INDEX(N_INTR_RXQ3_COMP)] |= MSINUM_INTR_SOURCE(1, N_INTR_RXQ3_COMP); - map[MSINUM_REG_INDEX(N_INTR_RXQ0_DESC_EMPTY)] = + map[MSINUM_REG_INDEX(N_INTR_RXQ0_DESC_EMPTY)] |= MSINUM_INTR_SOURCE(1, N_INTR_RXQ0_DESC_EMPTY); - map[MSINUM_REG_INDEX(N_INTR_RXQ1_DESC_EMPTY)] = + map[MSINUM_REG_INDEX(N_INTR_RXQ1_DESC_EMPTY)] |= MSINUM_INTR_SOURCE(1, N_INTR_RXQ1_DESC_EMPTY); - map[MSINUM_REG_INDEX(N_INTR_RXQ2_DESC_EMPTY)] = + map[MSINUM_REG_INDEX(N_INTR_RXQ2_DESC_EMPTY)] |= MSINUM_INTR_SOURCE(1, N_INTR_RXQ2_DESC_EMPTY); - map[MSINUM_REG_INDEX(N_INTR_RXQ3_DESC_EMPTY)] = + map[MSINUM_REG_INDEX(N_INTR_RXQ3_DESC_EMPTY)] |= MSINUM_INTR_SOURCE(1, N_INTR_RXQ3_DESC_EMPTY); - map[MSINUM_REG_INDEX(N_INTR_RXQ0_COAL)] = + map[MSINUM_REG_INDEX(N_INTR_RXQ0_COAL)] |= MSINUM_INTR_SOURCE(1, N_INTR_RXQ0_COAL); - map[MSINUM_REG_INDEX(N_INTR_RXQ1_COAL)] = + map[MSINUM_REG_INDEX(N_INTR_RXQ1_COAL)] |= MSINUM_INTR_SOURCE(1, N_INTR_RXQ1_COAL); - map[MSINUM_REG_INDEX(N_INTR_RXQ2_COAL)] = + map[MSINUM_REG_INDEX(N_INTR_RXQ2_COAL)] |= MSINUM_INTR_SOURCE(1, N_INTR_RXQ2_COAL); - map[MSINUM_REG_INDEX(N_INTR_RXQ3_COAL)] = + map[MSINUM_REG_INDEX(N_INTR_RXQ3_COAL)] |= MSINUM_INTR_SOURCE(1, N_INTR_RXQ3_COAL); - map[MSINUM_REG_INDEX(N_INTR_RXQ0_COAL_TO)] = + map[MSINUM_REG_INDEX(N_INTR_RXQ0_COAL_TO)] |= MSINUM_INTR_SOURCE(1, N_INTR_RXQ0_COAL_TO); - map[MSINUM_REG_INDEX(N_INTR_RXQ1_COAL_TO)] = + map[MSINUM_REG_INDEX(N_INTR_RXQ1_COAL_TO)] |= MSINUM_INTR_SOURCE(1, N_INTR_RXQ1_COAL_TO); - map[MSINUM_REG_INDEX(N_INTR_RXQ2_COAL_TO)] = + map[MSINUM_REG_INDEX(N_INTR_RXQ2_COAL_TO)] |= MSINUM_INTR_SOURCE(1, N_INTR_RXQ2_COAL_TO); - map[MSINUM_REG_INDEX(N_INTR_RXQ3_COAL_TO)] = + map[MSINUM_REG_INDEX(N_INTR_RXQ3_COAL_TO)] |= MSINUM_INTR_SOURCE(1, N_INTR_RXQ3_COAL_TO); /* Map all other interrupts source to MSI/MSIX vector 0. */