From owner-freebsd-hackers@FreeBSD.ORG Mon Nov 22 14:53:36 2010 Return-Path: Delivered-To: freebsd-hackers@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 741C31065674 for ; Mon, 22 Nov 2010 14:53:35 +0000 (UTC) (envelope-from jhb@freebsd.org) Received: from cyrus.watson.org (cyrus.watson.org [65.122.17.42]) by mx1.freebsd.org (Postfix) with ESMTP id 1E7128FC0A for ; Mon, 22 Nov 2010 14:53:35 +0000 (UTC) Received: from bigwig.baldwin.cx (66.111.2.69.static.nyinternet.net [66.111.2.69]) by cyrus.watson.org (Postfix) with ESMTPSA id AD70246B2E; Mon, 22 Nov 2010 09:53:34 -0500 (EST) Received: from jhbbsd.localnet (smtp.hudson-trading.com [209.249.190.9]) by bigwig.baldwin.cx (Postfix) with ESMTPSA id BD2A08A01D; Mon, 22 Nov 2010 09:53:33 -0500 (EST) From: John Baldwin To: freebsd-hackers@freebsd.org Date: Mon, 22 Nov 2010 09:20:15 -0500 User-Agent: KMail/1.13.5 (FreeBSD/7.3-CBSD-20101102; KDE/4.4.5; amd64; ; ) References: In-Reply-To: MIME-Version: 1.0 Content-Type: Text/Plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Message-Id: <201011220920.15431.jhb@freebsd.org> X-Greylist: Sender succeeded SMTP AUTH, not delayed by milter-greylist-4.2.6 (bigwig.baldwin.cx); Mon, 22 Nov 2010 09:53:33 -0500 (EST) X-Virus-Scanned: clamav-milter 0.96.3 at bigwig.baldwin.cx X-Virus-Status: Clean X-Spam-Status: No, score=-1.9 required=4.2 tests=BAYES_00 autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on bigwig.baldwin.cx Cc: Sergio =?iso-8859-1?q?Andr=E9s_G=F3mez_del_Real?= Subject: Re: Quick i386 question... X-BeenThere: freebsd-hackers@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Technical Discussions relating to FreeBSD List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 22 Nov 2010 14:53:36 -0000 On Saturday, November 20, 2010 3:38:58 pm Sergio Andr=E9s G=F3mez del Real = wrote: > If received an interrupt while in protected-mode and paging enabled, > is linear address from IDT stored at the idtr translated using the > paging-hierarchy structures? > I have looked at the interrupt/exception chapter in the corresponding > Intel manual but can't find the answer. Maybe I overlooked. Yes. A linear address is the flat virtual address after segments are taken= =20 into account. It is the address used as an input to the paging support in = the=20 MMU. =2D-=20 John Baldwin