From nobody Thu Nov 13 00:41:34 2025 X-Original-To: dev-commits-src-main@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id 4d6M0H0vYcz6GrTy; Thu, 13 Nov 2025 00:41:35 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "R12" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 4d6M0H0cyZz3J23; Thu, 13 Nov 2025 00:41:35 +0000 (UTC) (envelope-from git@FreeBSD.org) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1762994495; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=Mgfj+AFFR+gTCkSxaS6m+DATF+VZhHBJ/X0n7SlUnR8=; b=Z38EVszFxKzWm1dgpdFo6H2ARDxFLoP/vAyKcrJUNYQRAzmuSVAsMir6FBHVkVpWGIB9im w7eUIdJMvCMYO9G3jKtQEwz6p94qZmUXj98BldTJJyE5fNj35l6c+m92oia/APIMe4U9XV MB15zE6X9OeMtiFlysJ4UCs3IqKiliJLp2YzNQQvrZXocL/YRnyq4zSn3OqTyJ5V6aN0Ye w10UV3LDs6gLwzjHmz7OuOd4jJbVVFUYK8ALkL5wSmRRy1/feNslaOfMSwABXT1ZT3571Q fQYY25jup9oBXs5HACc6MoF2DSwpfMvetopjvfEg6zClKjbaEzkIuohrHL/UaQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1762994495; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=Mgfj+AFFR+gTCkSxaS6m+DATF+VZhHBJ/X0n7SlUnR8=; b=okKWi0rYgMmgTCX91Srb9VAc4dNRd16E1+0xDeOyI4xlRiULHMzHuTV6RdnsORiUqNYdHf QzSPQClui49yGX+EpR/Q5H9kKsuhJ6MMpLp0i/9svHsCQvW4YJG/L04n4FSQeVVfxpvYhl zFgw/T0KwXytuswoQlXVEZs1hqui6kNwdrCU6DUQVTFEr5egTdOzi6oA4446Xmq7QXXVQb ytiKnXhrjNEgFMR+NF+E9SSfvk9djEiroL+veZ6BWANwN/gaF8DMzzT1otgeY/NBFEk/J0 eV8He4qcwoFeoAQ6s1vFdUIop1pxBvkPA6fiynbCErS4dmyaY+wOWv5JOh5LTQ== ARC-Seal: i=1; s=dkim; d=freebsd.org; t=1762994495; a=rsa-sha256; cv=none; b=tymgCXSOQTgDG91+Viq7vf4yKjDBx5BpUgXeCNPYzarVd3ighjZ3ue7BcqAQ7OuUit34za VjfW5HnGZtvGk9qFAYsQuFVrX7cROXQOyLm+XPxU3GoEOu4xvNCj7Pk7lAnWvtCDv6qf71 GzfONVsV6Pk7k4J38+wiGs7lAK602hnWIS4OTXaMLSdadttDgvyZZNx86SunlChEI1fMKx 8Xyaymt0iNdWl+4QUpndCUCaMFiS2nRx5mbpRFV8JIOCNsoON5v681yyctjwbc8LdTkt0N 1WtrdnhYWXxrHM18dmAq7ndFCy8pFp149GXxsOIqfpdT+vK639oDF670fxprwA== ARC-Authentication-Results: i=1; mx1.freebsd.org; none Received: from gitrepo.freebsd.org (gitrepo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:5]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 4d6M0H08rszyBM; Thu, 13 Nov 2025 00:41:35 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from gitrepo.freebsd.org ([127.0.1.44]) by gitrepo.freebsd.org (8.18.1/8.18.1) with ESMTP id 5AD0fY1C077226; Thu, 13 Nov 2025 00:41:34 GMT (envelope-from git@gitrepo.freebsd.org) Received: (from git@localhost) by gitrepo.freebsd.org (8.18.1/8.18.1/Submit) id 5AD0fYXA077222; Thu, 13 Nov 2025 00:41:34 GMT (envelope-from git) Date: Thu, 13 Nov 2025 00:41:34 GMT Message-Id: <202511130041.5AD0fYXA077222@gitrepo.freebsd.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-main@FreeBSD.org From: Navdeep Parhar Subject: git: 17b4a0acfaf5 - main - cxgbe(4): T7 related updates to shared code List-Id: Commit messages for the main branch of the src repository List-Archive: https://lists.freebsd.org/archives/dev-commits-src-main List-Help: List-Post: List-Subscribe: List-Unsubscribe: X-BeenThere: dev-commits-src-main@freebsd.org Sender: owner-dev-commits-src-main@FreeBSD.org MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Git-Committer: np X-Git-Repository: src X-Git-Refname: refs/heads/main X-Git-Reftype: branch X-Git-Commit: 17b4a0acfaf5e58a04232c756a79d73649ead231 Auto-Submitted: auto-generated The branch main has been updated by np: URL: https://cgit.FreeBSD.org/src/commit/?id=17b4a0acfaf5e58a04232c756a79d73649ead231 commit 17b4a0acfaf5e58a04232c756a79d73649ead231 Author: Navdeep Parhar AuthorDate: 2025-10-15 19:29:06 +0000 Commit: Navdeep Parhar CommitDate: 2025-11-13 00:32:38 +0000 cxgbe(4): T7 related updates to shared code - Avoid some more registers with read side-effects during regdump. - mps_tcam_size is 3x the size of T6/T5. - Update rss_rd_row to work with T7. Obtained from: Chelsio Communications MFC after: 1 week Sponsored by: Chelsio Communications --- sys/dev/cxgbe/common/t4_hw.c | 98 +++++-- sys/dev/cxgbe/common/t4_msg.h | 566 +++++++++++++++++++++++++++++++++------ sys/dev/cxgbe/common/t4_regs.h | 100 ++++++- sys/dev/cxgbe/tom/t4_cpl_io.c | 2 +- usr.sbin/cxgbetool/reg_defs_t7.c | 126 +++++---- 5 files changed, 723 insertions(+), 169 deletions(-) diff --git a/sys/dev/cxgbe/common/t4_hw.c b/sys/dev/cxgbe/common/t4_hw.c index eb7ea9acc108..1fd1c36c1f25 100644 --- a/sys/dev/cxgbe/common/t4_hw.c +++ b/sys/dev/cxgbe/common/t4_hw.c @@ -84,6 +84,41 @@ static inline int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask, delay, NULL); } + /** + * t7_wait_sram_done - wait until an operation is completed + * @adapter: the adapter performing the operation + * @reg: the register to check for completion + * @result_reg: register that holds the result value + * @attempts: number of check iterations + * @delay: delay in usecs between iterations + * @valp: where to store the value of the result register at completion time + * + * Waits until a specific bit in @reg is cleared, checking up to + * @attempts times.Once the bit is cleared, reads from @result_reg + * and stores the value in @valp if it is not NULL. Returns 0 if the + * operation completes successfully and -EAGAIN if it times out. + */ +static int t7_wait_sram_done(struct adapter *adap, int reg, int result_reg, + int attempts, int delay, u32 *valp) +{ + while (1) { + u32 val = t4_read_reg(adap, reg); + + /* Check if SramStart (bit 19) is cleared */ + if (!(val & (1 << 19))) { + if (valp) + *valp = t4_read_reg(adap, result_reg); + return 0; + } + + if (--attempts == 0) + return -EAGAIN; + + if (delay) + udelay(delay); + } +} + /** * t4_set_reg_field - set a register field to a value * @adapter: the adapter to program @@ -578,14 +613,15 @@ int t4_mc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *ecc) mc_bist_cmd_len_reg = A_MC_BIST_CMD_LEN; mc_bist_status_rdata_reg = A_MC_BIST_STATUS_RDATA; mc_bist_data_pattern_reg = A_MC_BIST_DATA_PATTERN; - } else { + } else if (chip_id(adap) < CHELSIO_T7) { mc_bist_cmd_reg = MC_REG(A_MC_P_BIST_CMD, idx); mc_bist_cmd_addr_reg = MC_REG(A_MC_P_BIST_CMD_ADDR, idx); mc_bist_cmd_len_reg = MC_REG(A_MC_P_BIST_CMD_LEN, idx); - mc_bist_status_rdata_reg = MC_REG(A_MC_P_BIST_STATUS_RDATA, - idx); - mc_bist_data_pattern_reg = MC_REG(A_MC_P_BIST_DATA_PATTERN, - idx); + mc_bist_status_rdata_reg = MC_REG(A_MC_P_BIST_STATUS_RDATA, idx); + mc_bist_data_pattern_reg = MC_REG(A_MC_P_BIST_DATA_PATTERN, idx); + } else { + /* Need to figure out split mode and the rest. */ + return (-ENOTSUP); } if (t4_read_reg(adap, mc_bist_cmd_reg) & F_START_BIST) @@ -636,21 +672,13 @@ int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *ecc) edc_bist_status_rdata_reg = EDC_REG(A_EDC_BIST_STATUS_RDATA, idx); } else { -/* - * These macro are missing in t4_regs.h file. - * Added temporarily for testing. - */ -#define EDC_STRIDE_T5 (EDC_T51_BASE_ADDR - EDC_T50_BASE_ADDR) -#define EDC_REG_T5(reg, idx) (reg + EDC_STRIDE_T5 * idx) - edc_bist_cmd_reg = EDC_REG_T5(A_EDC_H_BIST_CMD, idx); - edc_bist_cmd_addr_reg = EDC_REG_T5(A_EDC_H_BIST_CMD_ADDR, idx); - edc_bist_cmd_len_reg = EDC_REG_T5(A_EDC_H_BIST_CMD_LEN, idx); - edc_bist_cmd_data_pattern = EDC_REG_T5(A_EDC_H_BIST_DATA_PATTERN, + edc_bist_cmd_reg = EDC_T5_REG(A_EDC_H_BIST_CMD, idx); + edc_bist_cmd_addr_reg = EDC_T5_REG(A_EDC_H_BIST_CMD_ADDR, idx); + edc_bist_cmd_len_reg = EDC_T5_REG(A_EDC_H_BIST_CMD_LEN, idx); + edc_bist_cmd_data_pattern = EDC_T5_REG(A_EDC_H_BIST_DATA_PATTERN, idx); - edc_bist_status_rdata_reg = EDC_REG_T5(A_EDC_H_BIST_STATUS_RDATA, + edc_bist_status_rdata_reg = EDC_T5_REG(A_EDC_H_BIST_STATUS_RDATA, idx); -#undef EDC_REG_T5 -#undef EDC_STRIDE_T5 } if (t4_read_reg(adap, edc_bist_cmd_reg) & F_START_BIST) @@ -2662,10 +2690,9 @@ void t4_get_regs(struct adapter *adap, u8 *buf, size_t buf_size) 0x173c, 0x1760, 0x1800, 0x18fc, 0x3000, 0x3044, - 0x3060, 0x3064, 0x30a4, 0x30b0, 0x30b8, 0x30d8, - 0x30e0, 0x30fc, + 0x30e0, 0x30e8, 0x3140, 0x357c, 0x35a8, 0x35cc, 0x35e0, 0x35ec, @@ -2680,7 +2707,7 @@ void t4_get_regs(struct adapter *adap, u8 *buf, size_t buf_size) 0x480c, 0x4814, 0x4890, 0x489c, 0x48a4, 0x48ac, - 0x48b8, 0x48c4, + 0x48b8, 0x48bc, 0x4900, 0x4924, 0x4ffc, 0x4ffc, 0x5500, 0x5624, @@ -2698,8 +2725,10 @@ void t4_get_regs(struct adapter *adap, u8 *buf, size_t buf_size) 0x5a60, 0x5a6c, 0x5a80, 0x5a8c, 0x5a94, 0x5a9c, - 0x5b94, 0x5bfc, - 0x5c10, 0x5e48, + 0x5b94, 0x5bec, + 0x5bf8, 0x5bfc, + 0x5c10, 0x5c40, + 0x5c4c, 0x5e48, 0x5e50, 0x5e94, 0x5ea0, 0x5eb0, 0x5ec0, 0x5ec0, @@ -2708,7 +2737,8 @@ void t4_get_regs(struct adapter *adap, u8 *buf, size_t buf_size) 0x5ef0, 0x5ef0, 0x5f00, 0x5f04, 0x5f0c, 0x5f10, - 0x5f20, 0x5f88, + 0x5f20, 0x5f78, + 0x5f84, 0x5f88, 0x5f90, 0x5fd8, 0x6000, 0x6020, 0x6028, 0x6030, @@ -3084,7 +3114,7 @@ void t4_get_regs(struct adapter *adap, u8 *buf, size_t buf_size) 0x38140, 0x38140, 0x38150, 0x38154, 0x38160, 0x381c4, - 0x381f0, 0x38204, + 0x381d0, 0x38204, 0x3820c, 0x38214, 0x3821c, 0x3822c, 0x38244, 0x38244, @@ -3156,6 +3186,10 @@ void t4_get_regs(struct adapter *adap, u8 *buf, size_t buf_size) 0x3a000, 0x3a004, 0x3a050, 0x3a084, 0x3a090, 0x3a09c, + 0x3a93c, 0x3a93c, + 0x3b93c, 0x3b93c, + 0x3c93c, 0x3c93c, + 0x3d93c, 0x3d93c, 0x3e000, 0x3e020, 0x3e03c, 0x3e05c, 0x3e100, 0x3e120, @@ -6439,9 +6473,15 @@ int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid, /* Read an RSS table row */ static int rd_rss_row(struct adapter *adap, int row, u32 *val) { - t4_write_reg(adap, A_TP_RSS_LKP_TABLE, 0xfff00000 | row); - return t4_wait_op_done_val(adap, A_TP_RSS_LKP_TABLE, F_LKPTBLROWVLD, 1, - 5, 0, val); + if (chip_id(adap) < CHELSIO_T7) { + t4_write_reg(adap, A_TP_RSS_LKP_TABLE, 0xfff00000 | row); + return t4_wait_op_done_val(adap, A_TP_RSS_LKP_TABLE, + F_LKPTBLROWVLD, 1, 5, 0, val); + } else { + t4_write_reg(adap, A_TP_RSS_CONFIG_SRAM, 0xB0000 | row); + return t7_wait_sram_done(adap, A_TP_RSS_CONFIG_SRAM, + A_TP_RSS_LKP_TABLE, 5, 0, val); + } } /** @@ -10178,7 +10218,7 @@ const struct chip_params *t4_get_chip_params(int chipid) .vfcount = 256, .sge_fl_db = 0, .sge_ctxt_size = SGE_CTXT_SIZE_T7, - .mps_tcam_size = NUM_MPS_T5_CLS_SRAM_L_INSTANCES, + .mps_tcam_size = NUM_MPS_T5_CLS_SRAM_L_INSTANCES * 3, .rss_nentries = T7_RSS_NENTRIES, .cim_la_size = CIMLA_SIZE_T6, }, diff --git a/sys/dev/cxgbe/common/t4_msg.h b/sys/dev/cxgbe/common/t4_msg.h index 0d12ccf2e910..214080964fbb 100644 --- a/sys/dev/cxgbe/common/t4_msg.h +++ b/sys/dev/cxgbe/common/t4_msg.h @@ -30,6 +30,7 @@ #define T4_MSG_H enum cpl_opcodes { + CPL_TLS_TX_SCMD_FMT = 0x0, CPL_PASS_OPEN_REQ = 0x1, CPL_PASS_ACCEPT_RPL = 0x2, CPL_ACT_OPEN_REQ = 0x3, @@ -48,6 +49,8 @@ enum cpl_opcodes { CPL_RTE_READ_REQ = 0x11, CPL_L2T_WRITE_REQ = 0x12, CPL_L2T_READ_REQ = 0x13, + CPL_GRE_TABLE_REQ = 0x1b, + CPL_GRE_TABLE_RPL = 0xbb, CPL_SMT_WRITE_REQ = 0x14, CPL_SMT_READ_REQ = 0x15, CPL_TAG_WRITE_REQ = 0x16, @@ -130,6 +133,7 @@ enum cpl_opcodes { CPL_TX_TLS_SFO = 0x89, CPL_TX_SEC_PDU = 0x8A, CPL_TX_TLS_ACK = 0x8B, + CPL_TX_QUIC_ENC = 0x8d, CPL_RCB_UPD = 0x8C, CPL_SGE_FLR_FLUSH = 0xA0, @@ -258,6 +262,7 @@ enum { ULP_MODE_TCPDDP = 5, ULP_MODE_FCOE = 6, ULP_MODE_TLS = 8, + ULP_MODE_DTLS = 9, ULP_MODE_RDMA_V2 = 10, ULP_MODE_NVMET = 11, }; @@ -1149,23 +1154,36 @@ struct cpl_get_tcb { #define V_QUEUENO(x) ((x) << S_QUEUENO) #define G_QUEUENO(x) (((x) >> S_QUEUENO) & M_QUEUENO) -#define S_T7_QUEUENO 0 -#define M_T7_QUEUENO 0xFFF -#define V_T7_QUEUENO(x) ((x) << S_T7_QUEUENO) -#define G_T7_QUEUENO(x) (((x) >> S_T7_QUEUENO) & M_T7_QUEUENO) - #define S_REPLY_CHAN 14 #define V_REPLY_CHAN(x) ((x) << S_REPLY_CHAN) #define F_REPLY_CHAN V_REPLY_CHAN(1U) +#define S_NO_REPLY 15 +#define V_NO_REPLY(x) ((x) << S_NO_REPLY) +#define F_NO_REPLY V_NO_REPLY(1U) + +struct cpl_t7_get_tcb { + WR_HDR; + union opcode_tid ot; + __be16 rxchan_queue; + __be16 cookie_pkd; +}; + #define S_T7_REPLY_CHAN 12 #define M_T7_REPLY_CHAN 0x7 #define V_T7_REPLY_CHAN(x) ((x) << S_T7_REPLY_CHAN) #define G_T7_REPLY_CHAN(x) (((x) >> S_T7_REPLY_CHAN) & M_T7_REPLY_CHAN) -#define S_NO_REPLY 15 -#define V_NO_REPLY(x) ((x) << S_NO_REPLY) -#define F_NO_REPLY V_NO_REPLY(1U) +#define S_T7_QUEUENO 0 +#define M_T7_QUEUENO 0xFFF +#define V_T7_QUEUENO(x) ((x) << S_T7_QUEUENO) +#define G_T7_QUEUENO(x) (((x) >> S_T7_QUEUENO) & M_T7_QUEUENO) + +#define S_CPL_GET_TCB_COOKIE 0 +#define M_CPL_GET_TCB_COOKIE 0xff +#define V_CPL_GET_TCB_COOKIE(x) ((x) << S_CPL_GET_TCB_COOKIE) +#define G_CPL_GET_TCB_COOKIE(x) \ + (((x) >> S_CPL_GET_TCB_COOKIE) & M_CPL_GET_TCB_COOKIE) struct cpl_get_tcb_rpl { RSS_HDR @@ -1234,6 +1252,16 @@ struct cpl_close_con_rpl { __be32 rcv_nxt; }; +struct cpl_t7_close_con_rpl { + RSS_HDR + union opcode_tid ot; + __be16 rto; + __u8 rsvd; + __u8 status; + __be32 snd_nxt; + __be32 rcv_nxt; +}; + struct cpl_close_listsvr_req { WR_HDR; union opcode_tid ot; @@ -1340,6 +1368,24 @@ struct cpl_abort_rpl_rss { __u8 status; }; +struct cpl_t7_abort_rpl_rss { + RSS_HDR + union opcode_tid ot; + __be32 idx_status; +}; + +#define S_CPL_ABORT_RPL_RSS_IDX 8 +#define M_CPL_ABORT_RPL_RSS_IDX 0xffffff +#define V_CPL_ABORT_RPL_RSS_IDX(x) ((x) << S_CPL_ABORT_RPL_RSS_IDX) +#define G_CPL_ABORT_RPL_RSS_IDX(x) \ + (((x) >> S_CPL_ABORT_RPL_RSS_IDX) & M_CPL_ABORT_RPL_RSS_IDX) + +#define S_CPL_ABORT_RPL_RSS_STATUS 0 +#define M_CPL_ABORT_RPL_RSS_STATUS 0xff +#define V_CPL_ABORT_RPL_RSS_STATUS(x) ((x) << S_CPL_ABORT_RPL_RSS_STATUS) +#define G_CPL_ABORT_RPL_RSS_STATUS(x) \ + (((x) >> S_CPL_ABORT_RPL_RSS_STATUS) & M_CPL_ABORT_RPL_RSS_STATUS) + struct cpl_abort_rpl_rss6 { RSS_HDR union opcode_tid ot; @@ -1444,6 +1490,11 @@ struct cpl_tx_data { #define V_TX_ULP_MODE(x) ((x) << S_TX_ULP_MODE) #define G_TX_ULP_MODE(x) (((x) >> S_TX_ULP_MODE) & M_TX_ULP_MODE) +#define S_T7_TX_ULP_MODE 10 +#define M_T7_TX_ULP_MODE 0xf +#define V_T7_TX_ULP_MODE(x) ((x) << S_T7_TX_ULP_MODE) +#define G_T7_TX_ULP_MODE(x) (((x) >> S_T7_TX_ULP_MODE) & M_T7_TX_ULP_MODE) + #define S_TX_FORCE 13 #define V_TX_FORCE(x) ((x) << S_TX_FORCE) #define F_TX_FORCE V_TX_FORCE(1U) @@ -1881,14 +1932,6 @@ struct cpl_tx_pkt_xt { (((x) >> S_CPL_TX_PKT_XT_ROCEIPHDRLEN_HI) & \ M_CPL_TX_PKT_XT_ROCEIPHDRLEN_HI) -#define S_CPL_TX_PKT_XT_ROCEIPHDRLEN_LO 30 -#define M_CPL_TX_PKT_XT_ROCEIPHDRLEN_LO 0x3 -#define V_CPL_TX_PKT_XT_ROCEIPHDRLEN_LO(x) \ - ((x) << S_CPL_TX_PKT_XT_ROCEIPHDRLEN_LO) -#define G_CPL_TX_PKT_XT_ROCEIPHDRLEN_LO(x) \ - (((x) >> S_CPL_TX_PKT_XT_ROCEIPHDRLEN_LO) & \ - M_CPL_TX_PKT_XT_ROCEIPHDRLEN_LO) - /* cpl_tx_pkt_xt.core.ctrl2 fields */ #define S_CPL_TX_PKT_XT_CHKINSRTOFFSET_LO 30 #define M_CPL_TX_PKT_XT_CHKINSRTOFFSET_LO 0x3 @@ -1898,6 +1941,14 @@ struct cpl_tx_pkt_xt { (((x) >> S_CPL_TX_PKT_XT_CHKINSRTOFFSET_LO) & \ M_CPL_TX_PKT_XT_CHKINSRTOFFSET_LO) +#define S_CPL_TX_PKT_XT_ROCEIPHDRLEN_LO 30 +#define M_CPL_TX_PKT_XT_ROCEIPHDRLEN_LO 0x3 +#define V_CPL_TX_PKT_XT_ROCEIPHDRLEN_LO(x) \ + ((x) << S_CPL_TX_PKT_XT_ROCEIPHDRLEN_LO) +#define G_CPL_TX_PKT_XT_ROCEIPHDRLEN_LO(x) \ + (((x) >> S_CPL_TX_PKT_XT_ROCEIPHDRLEN_LO) & \ + M_CPL_TX_PKT_XT_ROCEIPHDRLEN_LO) + #define S_CPL_TX_PKT_XT_CHKSTARTOFFSET 20 #define M_CPL_TX_PKT_XT_CHKSTARTOFFSET 0x3ff #define V_CPL_TX_PKT_XT_CHKSTARTOFFSET(x) \ @@ -2190,7 +2241,8 @@ struct cpl_t7_tx_data_iso { __be32 num_pi_bytes_seglen_offset; __be32 datasn_offset; __be32 buffer_offset; - __be32 reserved3; + __be32 pdo_pkd; + /* encapsulated CPL_TX_DATA follows here */ }; #define S_CPL_T7_TX_DATA_ISO_OPCODE 24 @@ -2274,6 +2326,12 @@ struct cpl_t7_tx_data_iso { (((x) >> S_CPL_T7_TX_DATA_ISO_DATASEGLENOFFSET) & \ M_CPL_T7_TX_DATA_ISO_DATASEGLENOFFSET) +#define S_CPL_TX_DATA_ISO_PDO 0 +#define M_CPL_TX_DATA_ISO_PDO 0xff +#define V_CPL_TX_DATA_ISO_PDO(x) ((x) << S_CPL_TX_DATA_ISO_PDO) +#define G_CPL_TX_DATA_ISO_PDO(x) \ + (((x) >> S_CPL_TX_DATA_ISO_PDO) & M_CPL_TX_DATA_ISO_PDO) + struct cpl_iscsi_hdr { RSS_HDR union opcode_tid ot; @@ -2419,6 +2477,74 @@ struct cpl_rx_data_ack_core { #define V_RX_DACK_CHANGE(x) ((x) << S_RX_DACK_CHANGE) #define F_RX_DACK_CHANGE V_RX_DACK_CHANGE(1U) +struct cpl_rx_phys_addr { + __be32 RSS[2]; + __be32 op_to_tid; + __be32 pci_rlx_order_to_len; + __be64 phys_addr; +}; + +#define S_CPL_RX_PHYS_ADDR_OPCODE 24 +#define M_CPL_RX_PHYS_ADDR_OPCODE 0xff +#define V_CPL_RX_PHYS_ADDR_OPCODE(x) ((x) << S_CPL_RX_PHYS_ADDR_OPCODE) +#define G_CPL_RX_PHYS_ADDR_OPCODE(x) \ + (((x) >> S_CPL_RX_PHYS_ADDR_OPCODE) & M_CPL_RX_PHYS_ADDR_OPCODE) + +#define S_CPL_RX_PHYS_ADDR_ISRDMA 23 +#define M_CPL_RX_PHYS_ADDR_ISRDMA 0x1 +#define V_CPL_RX_PHYS_ADDR_ISRDMA(x) ((x) << S_CPL_RX_PHYS_ADDR_ISRDMA) +#define G_CPL_RX_PHYS_ADDR_ISRDMA(x) \ + (((x) >> S_CPL_RX_PHYS_ADDR_ISRDMA) & M_CPL_RX_PHYS_ADDR_ISRDMA) +#define F_CPL_RX_PHYS_ADDR_ISRDMA V_CPL_RX_PHYS_ADDR_ISRDMA(1U) + +#define S_CPL_RX_PHYS_ADDR_TID 0 +#define M_CPL_RX_PHYS_ADDR_TID 0xfffff +#define V_CPL_RX_PHYS_ADDR_TID(x) ((x) << S_CPL_RX_PHYS_ADDR_TID) +#define G_CPL_RX_PHYS_ADDR_TID(x) \ + (((x) >> S_CPL_RX_PHYS_ADDR_TID) & M_CPL_RX_PHYS_ADDR_TID) + +#define S_CPL_RX_PHYS_ADDR_PCIRLXORDER 31 +#define M_CPL_RX_PHYS_ADDR_PCIRLXORDER 0x1 +#define V_CPL_RX_PHYS_ADDR_PCIRLXORDER(x) \ + ((x) << S_CPL_RX_PHYS_ADDR_PCIRLXORDER) +#define G_CPL_RX_PHYS_ADDR_PCIRLXORDER(x) \ + (((x) >> S_CPL_RX_PHYS_ADDR_PCIRLXORDER) & M_CPL_RX_PHYS_ADDR_PCIRLXORDER) +#define F_CPL_RX_PHYS_ADDR_PCIRLXORDER V_CPL_RX_PHYS_ADDR_PCIRLXORDER(1U) + +#define S_CPL_RX_PHYS_ADDR_PCINOSNOOP 30 +#define M_CPL_RX_PHYS_ADDR_PCINOSNOOP 0x1 +#define V_CPL_RX_PHYS_ADDR_PCINOSNOOP(x) \ + ((x) << S_CPL_RX_PHYS_ADDR_PCINOSNOOP) +#define G_CPL_RX_PHYS_ADDR_PCINOSNOOP(x) \ + (((x) >> S_CPL_RX_PHYS_ADDR_PCINOSNOOP) & M_CPL_RX_PHYS_ADDR_PCINOSNOOP) +#define F_CPL_RX_PHYS_ADDR_PCINOSNOOP V_CPL_RX_PHYS_ADDR_PCINOSNOOP(1U) + +#define S_CPL_RX_PHYS_ADDR_PCITPHINTEN 29 +#define M_CPL_RX_PHYS_ADDR_PCITPHINTEN 0x1 +#define V_CPL_RX_PHYS_ADDR_PCITPHINTEN(x) \ + ((x) << S_CPL_RX_PHYS_ADDR_PCITPHINTEN) +#define G_CPL_RX_PHYS_ADDR_PCITPHINTEN(x) \ + (((x) >> S_CPL_RX_PHYS_ADDR_PCITPHINTEN) & M_CPL_RX_PHYS_ADDR_PCITPHINTEN) +#define F_CPL_RX_PHYS_ADDR_PCITPHINTEN V_CPL_RX_PHYS_ADDR_PCITPHINTEN(1U) + +#define S_CPL_RX_PHYS_ADDR_PCITPHINT 27 +#define M_CPL_RX_PHYS_ADDR_PCITPHINT 0x3 +#define V_CPL_RX_PHYS_ADDR_PCITPHINT(x) ((x) << S_CPL_RX_PHYS_ADDR_PCITPHINT) +#define G_CPL_RX_PHYS_ADDR_PCITPHINT(x) \ + (((x) >> S_CPL_RX_PHYS_ADDR_PCITPHINT) & M_CPL_RX_PHYS_ADDR_PCITPHINT) + +#define S_CPL_RX_PHYS_ADDR_DCAID 16 +#define M_CPL_RX_PHYS_ADDR_DCAID 0x7ff +#define V_CPL_RX_PHYS_ADDR_DCAID(x) ((x) << S_CPL_RX_PHYS_ADDR_DCAID) +#define G_CPL_RX_PHYS_ADDR_DCAID(x) \ + (((x) >> S_CPL_RX_PHYS_ADDR_DCAID) & M_CPL_RX_PHYS_ADDR_DCAID) + +#define S_CPL_RX_PHYS_ADDR_LEN 0 +#define M_CPL_RX_PHYS_ADDR_LEN 0xffff +#define V_CPL_RX_PHYS_ADDR_LEN(x) ((x) << S_CPL_RX_PHYS_ADDR_LEN) +#define G_CPL_RX_PHYS_ADDR_LEN(x) \ + (((x) >> S_CPL_RX_PHYS_ADDR_LEN) & M_CPL_RX_PHYS_ADDR_LEN) + struct cpl_rx_ddp_complete { RSS_HDR union opcode_tid ot; @@ -4059,13 +4185,6 @@ struct cpl_rdma_cqe_ext { #define G_CPL_RDMA_CQE_EXT_QPID(x) \ (((x) >> S_CPL_RDMA_CQE_EXT_QPID) & M_CPL_RDMA_CQE_EXT_QPID) -#define S_CPL_RDMA_CQE_EXT_EXTMODE 11 -#define M_CPL_RDMA_CQE_EXT_EXTMODE 0x1 -#define V_CPL_RDMA_CQE_EXT_EXTMODE(x) ((x) << S_CPL_RDMA_CQE_EXT_EXTMODE) -#define G_CPL_RDMA_CQE_EXT_EXTMODE(x) \ - (((x) >> S_CPL_RDMA_CQE_EXT_EXTMODE) & M_CPL_RDMA_CQE_EXT_EXTMODE) -#define F_CPL_RDMA_CQE_EXT_EXTMODE V_CPL_RDMA_CQE_EXT_EXTMODE(1U) - #define S_CPL_RDMA_CQE_EXT_GENERATION_BIT 10 #define M_CPL_RDMA_CQE_EXT_GENERATION_BIT 0x1 #define V_CPL_RDMA_CQE_EXT_GENERATION_BIT(x) \ @@ -4109,6 +4228,13 @@ struct cpl_rdma_cqe_ext { #define G_CPL_RDMA_CQE_EXT_WR_TYPE_EXT(x) \ (((x) >> S_CPL_RDMA_CQE_EXT_WR_TYPE_EXT) & M_CPL_RDMA_CQE_EXT_WR_TYPE_EXT) +#define S_CPL_RDMA_CQE_EXT_EXTMODE 23 +#define M_CPL_RDMA_CQE_EXT_EXTMODE 0x1 +#define V_CPL_RDMA_CQE_EXT_EXTMODE(x) ((x) << S_CPL_RDMA_CQE_EXT_EXTMODE) +#define G_CPL_RDMA_CQE_EXT_EXTMODE(x) \ + (((x) >> S_CPL_RDMA_CQE_EXT_EXTMODE) & M_CPL_RDMA_CQE_EXT_EXTMODE) +#define F_CPL_RDMA_CQE_EXT_EXTMODE V_CPL_RDMA_CQE_EXT_EXTMODE(1U) + #define S_CPL_RDMA_CQE_EXT_SRQ 0 #define M_CPL_RDMA_CQE_EXT_SRQ 0xfff #define V_CPL_RDMA_CQE_EXT_SRQ(x) ((x) << S_CPL_RDMA_CQE_EXT_SRQ) @@ -4161,14 +4287,6 @@ struct cpl_rdma_cqe_fw_ext { #define G_CPL_RDMA_CQE_FW_EXT_QPID(x) \ (((x) >> S_CPL_RDMA_CQE_FW_EXT_QPID) & M_CPL_RDMA_CQE_FW_EXT_QPID) -#define S_CPL_RDMA_CQE_FW_EXT_EXTMODE 11 -#define M_CPL_RDMA_CQE_FW_EXT_EXTMODE 0x1 -#define V_CPL_RDMA_CQE_FW_EXT_EXTMODE(x) \ - ((x) << S_CPL_RDMA_CQE_FW_EXT_EXTMODE) -#define G_CPL_RDMA_CQE_FW_EXT_EXTMODE(x) \ - (((x) >> S_CPL_RDMA_CQE_FW_EXT_EXTMODE) & M_CPL_RDMA_CQE_FW_EXT_EXTMODE) -#define F_CPL_RDMA_CQE_FW_EXT_EXTMODE V_CPL_RDMA_CQE_FW_EXT_EXTMODE(1U) - #define S_CPL_RDMA_CQE_FW_EXT_GENERATION_BIT 10 #define M_CPL_RDMA_CQE_FW_EXT_GENERATION_BIT 0x1 #define V_CPL_RDMA_CQE_FW_EXT_GENERATION_BIT(x) \ @@ -4215,6 +4333,14 @@ struct cpl_rdma_cqe_fw_ext { (((x) >> S_CPL_RDMA_CQE_FW_EXT_WR_TYPE_EXT) & \ M_CPL_RDMA_CQE_FW_EXT_WR_TYPE_EXT) +#define S_CPL_RDMA_CQE_FW_EXT_EXTMODE 23 +#define M_CPL_RDMA_CQE_FW_EXT_EXTMODE 0x1 +#define V_CPL_RDMA_CQE_FW_EXT_EXTMODE(x) \ + ((x) << S_CPL_RDMA_CQE_FW_EXT_EXTMODE) +#define G_CPL_RDMA_CQE_FW_EXT_EXTMODE(x) \ + (((x) >> S_CPL_RDMA_CQE_FW_EXT_EXTMODE) & M_CPL_RDMA_CQE_FW_EXT_EXTMODE) +#define F_CPL_RDMA_CQE_FW_EXT_EXTMODE V_CPL_RDMA_CQE_FW_EXT_EXTMODE(1U) + #define S_CPL_RDMA_CQE_FW_EXT_SRQ 0 #define M_CPL_RDMA_CQE_FW_EXT_SRQ 0xfff #define V_CPL_RDMA_CQE_FW_EXT_SRQ(x) ((x) << S_CPL_RDMA_CQE_FW_EXT_SRQ) @@ -4267,14 +4393,6 @@ struct cpl_rdma_cqe_err_ext { #define G_CPL_RDMA_CQE_ERR_EXT_QPID(x) \ (((x) >> S_CPL_RDMA_CQE_ERR_EXT_QPID) & M_CPL_RDMA_CQE_ERR_EXT_QPID) -#define S_CPL_RDMA_CQE_ERR_EXT_EXTMODE 11 -#define M_CPL_RDMA_CQE_ERR_EXT_EXTMODE 0x1 -#define V_CPL_RDMA_CQE_ERR_EXT_EXTMODE(x) \ - ((x) << S_CPL_RDMA_CQE_ERR_EXT_EXTMODE) -#define G_CPL_RDMA_CQE_ERR_EXT_EXTMODE(x) \ - (((x) >> S_CPL_RDMA_CQE_ERR_EXT_EXTMODE) & M_CPL_RDMA_CQE_ERR_EXT_EXTMODE) -#define F_CPL_RDMA_CQE_ERR_EXT_EXTMODE V_CPL_RDMA_CQE_ERR_EXT_EXTMODE(1U) - #define S_CPL_RDMA_CQE_ERR_EXT_GENERATION_BIT 10 #define M_CPL_RDMA_CQE_ERR_EXT_GENERATION_BIT 0x1 #define V_CPL_RDMA_CQE_ERR_EXT_GENERATION_BIT(x) \ @@ -4323,6 +4441,14 @@ struct cpl_rdma_cqe_err_ext { (((x) >> S_CPL_RDMA_CQE_ERR_EXT_WR_TYPE_EXT) & \ M_CPL_RDMA_CQE_ERR_EXT_WR_TYPE_EXT) +#define S_CPL_RDMA_CQE_ERR_EXT_EXTMODE 23 +#define M_CPL_RDMA_CQE_ERR_EXT_EXTMODE 0x1 +#define V_CPL_RDMA_CQE_ERR_EXT_EXTMODE(x) \ + ((x) << S_CPL_RDMA_CQE_ERR_EXT_EXTMODE) +#define G_CPL_RDMA_CQE_ERR_EXT_EXTMODE(x) \ + (((x) >> S_CPL_RDMA_CQE_ERR_EXT_EXTMODE) & M_CPL_RDMA_CQE_ERR_EXT_EXTMODE) +#define F_CPL_RDMA_CQE_ERR_EXT_EXTMODE V_CPL_RDMA_CQE_ERR_EXT_EXTMODE(1U) + #define S_CPL_RDMA_CQE_ERR_EXT_SRQ 0 #define M_CPL_RDMA_CQE_ERR_EXT_SRQ 0xfff #define V_CPL_RDMA_CQE_ERR_EXT_SRQ(x) ((x) << S_CPL_RDMA_CQE_ERR_EXT_SRQ) @@ -5040,6 +5166,58 @@ struct cpl_tx_tnl_lso { #define G_CPL_TX_TNL_LSO_SIZE(x) \ (((x) >> S_CPL_TX_TNL_LSO_SIZE) & M_CPL_TX_TNL_LSO_SIZE) +#define S_CPL_TX_TNL_LSO_BTH_OPCODE 24 +#define M_CPL_TX_TNL_LSO_BTH_OPCODE 0xff +#define V_CPL_TX_TNL_LSO_BTH_OPCODE(x) ((x) << S_CPL_TX_TNL_LSO_BTH_OPCODE) +#define G_CPL_TX_TNL_LSO_BTH_OPCODE(x) \ + (((x) >> S_CPL_TX_TNL_LSO_BTH_OPCODE) & \ + M_CPL_TX_TNL_LSO_BTH_OPCODE) + +#define S_CPL_TX_TNL_LSO_TCPSEQOFFSET_PSN 0 +#define M_CPL_TX_TNL_LSO_TCPSEQOFFSET_PSN 0xffffff +#define V_CPL_TX_TNL_LSO_TCPSEQOFFSET_PSN(x) \ + ((x) << S_CPL_TX_TNL_LSO_TCPSEQOFFSET_PSN) +#define G_CPL_TX_TNL_LSO_TCPSEQOFFSET_PSN(x) \ + (((x) >> S_CPL_TX_TNL_LSO_TCPSEQOFFSET_PSN) & \ + M_CPL_TX_TNL_LSO_TCPSEQOFFSET_PSN) + +#define S_CPL_TX_TNL_LSO_MSS_TVER 8 +#define M_CPL_TX_TNL_LSO_MSS_TVER 0xf +#define V_CPL_TX_TNL_LSO_MSS_TVER(x) ((x) << S_CPL_TX_TNL_LSO_MSS_TVER) +#define G_CPL_TX_TNL_LSO_MSS_TVER(x) \ + (((x) >> S_CPL_TX_TNL_LSO_MSS_TVER) & M_CPL_TX_TNL_LSO_MSS_TVER) + +#define S_CPL_TX_TNL_LSO_MSS_M 7 +#define M_CPL_TX_TNL_LSO_MSS_M 0x1 +#define V_CPL_TX_TNL_LSO_MSS_M(x) ((x) << S_CPL_TX_TNL_LSO_MSS_M) +#define G_CPL_TX_TNL_LSO_MSS_M(x) \ + (((x) >> S_CPL_TX_TNL_LSO_MSS_M) & M_CPL_TX_TNL_LSO_MSS_M) + +#define S_CPL_TX_TNL_LSO_MSS_PMTU 4 +#define M_CPL_TX_TNL_LSO_MSS_PMTU 0x7 +#define V_CPL_TX_TNL_LSO_MSS_PMTU(x) ((x) << S_CPL_TX_TNL_LSO_MSS_PMTU) +#define G_CPL_TX_TNL_LSO_MSS_PMTU(x) \ + (((x) >> S_CPL_TX_TNL_LSO_MSS_PMTU) & M_CPL_TX_TNL_LSO_MSS_PMTU) + +#define S_CPL_TX_TNL_LSO_MSS_RR_MSN_INCR 3 +#define M_CPL_TX_TNL_LSO_MSS_RR_MSN_INCR 0x1 +#define V_CPL_TX_TNL_LSO_MSS_RR_MSN_INCR(x) \ + ((x) << S_CPL_TX_TNL_LSO_MSS_RR_MSN_INCR) +#define G_CPL_TX_TNL_LSO_MSS_RR_MSN_INCR(x) \ + (((x) >> S_CPL_TX_TNL_LSO_MSS_RR_MSN_INCR) & M_CPL_TX_TNL_LSO_MSS_RR_MSN_INCR) + +#define S_CPL_TX_TNL_LSO_MSS_ACKREQ 1 +#define M_CPL_TX_TNL_LSO_MSS_ACKREQ 0x3 +#define V_CPL_TX_TNL_LSO_MSS_ACKREQ(x) ((x) << S_CPL_TX_TNL_LSO_MSS_ACKREQ) +#define G_CPL_TX_TNL_LSO_MSS_ACKREQ(x) \ + (((x) >> S_CPL_TX_TNL_LSO_MSS_ACKREQ) & M_CPL_TX_TNL_LSO_MSS_ACKREQ) + +#define S_CPL_TX_TNL_LSO_MSS_SE 0 +#define M_CPL_TX_TNL_LSO_MSS_SE 0x1 +#define V_CPL_TX_TNL_LSO_MSS_SE(x) ((x) << S_CPL_TX_TNL_LSO_MSS_SE) +#define G_CPL_TX_TNL_LSO_MSS_SE(x) \ + (((x) >> S_CPL_TX_TNL_LSO_MSS_SE) & M_CPL_TX_TNL_LSO_MSS_SE) + struct cpl_rx_mps_pkt { __be32 op_to_r1_hi; __be32 r1_lo_length; @@ -5839,10 +6017,10 @@ struct cpl_tx_tls_ack { #define G_CPL_TX_TLS_ACK_OPCODE(x) \ (((x) >> S_CPL_TX_TLS_ACK_OPCODE) & M_CPL_TX_TLS_ACK_OPCODE) -#define S_T7_CPL_TX_TLS_ACK_RXCHID 22 -#define M_T7_CPL_TX_TLS_ACK_RXCHID 0x3 -#define V_T7_CPL_TX_TLS_ACK_RXCHID(x) ((x) << S_T7_CPL_TX_TLS_ACK_RXCHID) -#define G_T7_CPL_TX_TLS_ACK_RXCHID(x) \ +#define S_T7_CPL_TX_TLS_ACK_RXCHID 22 +#define M_T7_CPL_TX_TLS_ACK_RXCHID 0x3 +#define V_T7_CPL_TX_TLS_ACK_RXCHID(x) ((x) << S_T7_CPL_TX_TLS_ACK_RXCHID) +#define G_T7_CPL_TX_TLS_ACK_RXCHID(x) \ (((x) >> S_T7_CPL_TX_TLS_ACK_RXCHID) & M_T7_CPL_TX_TLS_ACK_RXCHID) #define S_CPL_TX_TLS_ACK_RXCHID 22 @@ -5905,11 +6083,245 @@ struct cpl_tx_tls_ack { #define G_CPL_TX_TLS_ACK_PLDLEN(x) \ (((x) >> S_CPL_TX_TLS_ACK_PLDLEN) & M_CPL_TX_TLS_ACK_PLDLEN) +struct cpl_tx_quic_enc { + __be32 op_to_hdrlen; + __be32 hdrlen_to_pktlen; + __be32 r4[2]; +}; + +#define S_CPL_TX_QUIC_ENC_OPCODE 24 +#define M_CPL_TX_QUIC_ENC_OPCODE 0xff +#define V_CPL_TX_QUIC_ENC_OPCODE(x) ((x) << S_CPL_TX_QUIC_ENC_OPCODE) +#define G_CPL_TX_QUIC_ENC_OPCODE(x) \ + (((x) >> S_CPL_TX_QUIC_ENC_OPCODE) & M_CPL_TX_QUIC_ENC_OPCODE) + +#define S_CPL_TX_QUIC_ENC_KEYSIZE 22 +#define M_CPL_TX_QUIC_ENC_KEYSIZE 0x3 +#define V_CPL_TX_QUIC_ENC_KEYSIZE(x) ((x) << S_CPL_TX_QUIC_ENC_KEYSIZE) +#define G_CPL_TX_QUIC_ENC_KEYSIZE(x) \ + (((x) >> S_CPL_TX_QUIC_ENC_KEYSIZE) & M_CPL_TX_QUIC_ENC_KEYSIZE) + +#define S_CPL_TX_QUIC_ENC_PKTNUMSIZE 20 +#define M_CPL_TX_QUIC_ENC_PKTNUMSIZE 0x3 +#define V_CPL_TX_QUIC_ENC_PKTNUMSIZE(x) ((x) << S_CPL_TX_QUIC_ENC_PKTNUMSIZE) +#define G_CPL_TX_QUIC_ENC_PKTNUMSIZE(x) \ + (((x) >> S_CPL_TX_QUIC_ENC_PKTNUMSIZE) & M_CPL_TX_QUIC_ENC_PKTNUMSIZE) + +#define S_CPL_TX_QUIC_ENC_HDRTYPE 19 +#define M_CPL_TX_QUIC_ENC_HDRTYPE 0x1 +#define V_CPL_TX_QUIC_ENC_HDRTYPE(x) ((x) << S_CPL_TX_QUIC_ENC_HDRTYPE) +#define G_CPL_TX_QUIC_ENC_HDRTYPE(x) \ + (((x) >> S_CPL_TX_QUIC_ENC_HDRTYPE) & M_CPL_TX_QUIC_ENC_HDRTYPE) +#define F_CPL_TX_QUIC_ENC_HDRTYPE V_CPL_TX_QUIC_ENC_HDRTYPE(1U) + +#define S_CPL_TX_QUIC_ENC_HDRSTARTOFFSET 4 +#define M_CPL_TX_QUIC_ENC_HDRSTARTOFFSET 0xfff +#define V_CPL_TX_QUIC_ENC_HDRSTARTOFFSET(x) \ + ((x) << S_CPL_TX_QUIC_ENC_HDRSTARTOFFSET) +#define G_CPL_TX_QUIC_ENC_HDRSTARTOFFSET(x) \ + (((x) >> S_CPL_TX_QUIC_ENC_HDRSTARTOFFSET) & \ + M_CPL_TX_QUIC_ENC_HDRSTARTOFFSET) + +#define S_CPL_TX_QUIC_ENC_HDRLENGTH_HI 0 +#define M_CPL_TX_QUIC_ENC_HDRLENGTH_HI 0x3 +#define V_CPL_TX_QUIC_ENC_HDRLENGTH_HI(x) \ + ((x) << S_CPL_TX_QUIC_ENC_HDRLENGTH_HI) +#define G_CPL_TX_QUIC_ENC_HDRLENGTH_HI(x) \ + (((x) >> S_CPL_TX_QUIC_ENC_HDRLENGTH_HI) & M_CPL_TX_QUIC_ENC_HDRLENGTH_HI) + +#define S_CPL_TX_QUIC_ENC_HDRLENGTH_LO 24 +#define M_CPL_TX_QUIC_ENC_HDRLENGTH_LO 0xff +#define V_CPL_TX_QUIC_ENC_HDRLENGTH_LO(x) \ + ((x) << S_CPL_TX_QUIC_ENC_HDRLENGTH_LO) +#define G_CPL_TX_QUIC_ENC_HDRLENGTH_LO(x) \ + (((x) >> S_CPL_TX_QUIC_ENC_HDRLENGTH_LO) & M_CPL_TX_QUIC_ENC_HDRLENGTH_LO) + +#define S_CPL_TX_QUIC_ENC_NUMPKT 16 +#define M_CPL_TX_QUIC_ENC_NUMPKT 0xff +#define V_CPL_TX_QUIC_ENC_NUMPKT(x) ((x) << S_CPL_TX_QUIC_ENC_NUMPKT) +#define G_CPL_TX_QUIC_ENC_NUMPKT(x) \ + (((x) >> S_CPL_TX_QUIC_ENC_NUMPKT) & M_CPL_TX_QUIC_ENC_NUMPKT) + +#define S_CPL_TX_QUIC_ENC_PKTLEN 0 +#define M_CPL_TX_QUIC_ENC_PKTLEN 0xffff +#define V_CPL_TX_QUIC_ENC_PKTLEN(x) ((x) << S_CPL_TX_QUIC_ENC_PKTLEN) +#define G_CPL_TX_QUIC_ENC_PKTLEN(x) \ + (((x) >> S_CPL_TX_QUIC_ENC_PKTLEN) & M_CPL_TX_QUIC_ENC_PKTLEN) + +struct cpl_tls_tx_scmd_fmt { + __be32 op_to_num_ivs; + __be32 enb_dbgId_to_hdrlen; + __be32 seq_num[2]; +}; + +#define S_CPL_TLS_TX_SCMD_FMT_OPCODE 31 +#define M_CPL_TLS_TX_SCMD_FMT_OPCODE 0x1 +#define V_CPL_TLS_TX_SCMD_FMT_OPCODE(x) ((x) << S_CPL_TLS_TX_SCMD_FMT_OPCODE) +#define G_CPL_TLS_TX_SCMD_FMT_OPCODE(x) \ + (((x) >> S_CPL_TLS_TX_SCMD_FMT_OPCODE) & M_CPL_TLS_TX_SCMD_FMT_OPCODE) +#define F_CPL_TLS_TX_SCMD_FMT_OPCODE V_CPL_TLS_TX_SCMD_FMT_OPCODE(1U) + +#define S_CPL_TLS_TX_SCMD_FMT_SEQNUMBERCTRL 29 +#define M_CPL_TLS_TX_SCMD_FMT_SEQNUMBERCTRL 0x3 +#define V_CPL_TLS_TX_SCMD_FMT_SEQNUMBERCTRL(x) \ + ((x) << S_CPL_TLS_TX_SCMD_FMT_SEQNUMBERCTRL) +#define G_CPL_TLS_TX_SCMD_FMT_SEQNUMBERCTRL(x) \ + (((x) >> S_CPL_TLS_TX_SCMD_FMT_SEQNUMBERCTRL) & \ + M_CPL_TLS_TX_SCMD_FMT_SEQNUMBERCTRL) + +#define S_CPL_TLS_TX_SCMD_FMT_PROTOVERSION 24 +#define M_CPL_TLS_TX_SCMD_FMT_PROTOVERSION 0xf +#define V_CPL_TLS_TX_SCMD_FMT_PROTOVERSION(x) \ + ((x) << S_CPL_TLS_TX_SCMD_FMT_PROTOVERSION) +#define G_CPL_TLS_TX_SCMD_FMT_PROTOVERSION(x) \ + (((x) >> S_CPL_TLS_TX_SCMD_FMT_PROTOVERSION) & \ + M_CPL_TLS_TX_SCMD_FMT_PROTOVERSION) + +#define S_CPL_TLS_TX_SCMD_FMT_ENCDECCTRL 23 +#define M_CPL_TLS_TX_SCMD_FMT_ENCDECCTRL 0x1 +#define V_CPL_TLS_TX_SCMD_FMT_ENCDECCTRL(x) \ + ((x) << S_CPL_TLS_TX_SCMD_FMT_ENCDECCTRL) +#define G_CPL_TLS_TX_SCMD_FMT_ENCDECCTRL(x) \ + (((x) >> S_CPL_TLS_TX_SCMD_FMT_ENCDECCTRL) & \ + M_CPL_TLS_TX_SCMD_FMT_ENCDECCTRL) +#define F_CPL_TLS_TX_SCMD_FMT_ENCDECCTRL V_CPL_TLS_TX_SCMD_FMT_ENCDECCTRL(1U) + +#define S_CPL_TLS_TX_SCMD_FMT_CIPHAUTHSEQCTRL 22 +#define M_CPL_TLS_TX_SCMD_FMT_CIPHAUTHSEQCTRL 0x1 +#define V_CPL_TLS_TX_SCMD_FMT_CIPHAUTHSEQCTRL(x) \ + ((x) << S_CPL_TLS_TX_SCMD_FMT_CIPHAUTHSEQCTRL) +#define G_CPL_TLS_TX_SCMD_FMT_CIPHAUTHSEQCTRL(x) \ + (((x) >> S_CPL_TLS_TX_SCMD_FMT_CIPHAUTHSEQCTRL) & \ + M_CPL_TLS_TX_SCMD_FMT_CIPHAUTHSEQCTRL) +#define F_CPL_TLS_TX_SCMD_FMT_CIPHAUTHSEQCTRL \ + V_CPL_TLS_TX_SCMD_FMT_CIPHAUTHSEQCTRL(1U) + +#define S_CPL_TLS_TX_SCMD_FMT_CIPHMODE 18 +#define M_CPL_TLS_TX_SCMD_FMT_CIPHMODE 0xf +#define V_CPL_TLS_TX_SCMD_FMT_CIPHMODE(x) \ + ((x) << S_CPL_TLS_TX_SCMD_FMT_CIPHMODE) +#define G_CPL_TLS_TX_SCMD_FMT_CIPHMODE(x) \ + (((x) >> S_CPL_TLS_TX_SCMD_FMT_CIPHMODE) & M_CPL_TLS_TX_SCMD_FMT_CIPHMODE) + +#define S_CPL_TLS_TX_SCMD_FMT_AUTHMODE 14 +#define M_CPL_TLS_TX_SCMD_FMT_AUTHMODE 0xf +#define V_CPL_TLS_TX_SCMD_FMT_AUTHMODE(x) \ + ((x) << S_CPL_TLS_TX_SCMD_FMT_AUTHMODE) +#define G_CPL_TLS_TX_SCMD_FMT_AUTHMODE(x) \ + (((x) >> S_CPL_TLS_TX_SCMD_FMT_AUTHMODE) & M_CPL_TLS_TX_SCMD_FMT_AUTHMODE) + +#define S_CPL_TLS_TX_SCMD_FMT_HMACCTRL 11 +#define M_CPL_TLS_TX_SCMD_FMT_HMACCTRL 0x7 +#define V_CPL_TLS_TX_SCMD_FMT_HMACCTRL(x) \ + ((x) << S_CPL_TLS_TX_SCMD_FMT_HMACCTRL) +#define G_CPL_TLS_TX_SCMD_FMT_HMACCTRL(x) \ + (((x) >> S_CPL_TLS_TX_SCMD_FMT_HMACCTRL) & M_CPL_TLS_TX_SCMD_FMT_HMACCTRL) + +#define S_CPL_TLS_TX_SCMD_FMT_IVSIZE 7 +#define M_CPL_TLS_TX_SCMD_FMT_IVSIZE 0xf +#define V_CPL_TLS_TX_SCMD_FMT_IVSIZE(x) ((x) << S_CPL_TLS_TX_SCMD_FMT_IVSIZE) +#define G_CPL_TLS_TX_SCMD_FMT_IVSIZE(x) \ + (((x) >> S_CPL_TLS_TX_SCMD_FMT_IVSIZE) & M_CPL_TLS_TX_SCMD_FMT_IVSIZE) + +#define S_CPL_TLS_TX_SCMD_FMT_NUMIVS 0 +#define M_CPL_TLS_TX_SCMD_FMT_NUMIVS 0x7f +#define V_CPL_TLS_TX_SCMD_FMT_NUMIVS(x) ((x) << S_CPL_TLS_TX_SCMD_FMT_NUMIVS) +#define G_CPL_TLS_TX_SCMD_FMT_NUMIVS(x) \ + (((x) >> S_CPL_TLS_TX_SCMD_FMT_NUMIVS) & M_CPL_TLS_TX_SCMD_FMT_NUMIVS) + +#define S_CPL_TLS_TX_SCMD_FMT_ENBDBGID 31 +#define M_CPL_TLS_TX_SCMD_FMT_ENBDBGID 0x1 +#define V_CPL_TLS_TX_SCMD_FMT_ENBDBGID(x) \ + ((x) << S_CPL_TLS_TX_SCMD_FMT_ENBDBGID) +#define G_CPL_TLS_TX_SCMD_FMT_ENBDBGID(x) \ + (((x) >> S_CPL_TLS_TX_SCMD_FMT_ENBDBGID) & M_CPL_TLS_TX_SCMD_FMT_ENBDBGID) +#define F_CPL_TLS_TX_SCMD_FMT_ENBDBGID V_CPL_TLS_TX_SCMD_FMT_ENBDBGID(1U) + +#define S_CPL_TLS_TX_SCMD_FMT_IVGENCTRL 30 +#define M_CPL_TLS_TX_SCMD_FMT_IVGENCTRL 0x1 +#define V_CPL_TLS_TX_SCMD_FMT_IVGENCTRL(x) \ + ((x) << S_CPL_TLS_TX_SCMD_FMT_IVGENCTRL) +#define G_CPL_TLS_TX_SCMD_FMT_IVGENCTRL(x) \ + (((x) >> S_CPL_TLS_TX_SCMD_FMT_IVGENCTRL) & \ + M_CPL_TLS_TX_SCMD_FMT_IVGENCTRL) + +#define S_CPL_TLS_TX_SCMD_FMT_MOREFRAGS 20 +#define M_CPL_TLS_TX_SCMD_FMT_MOREFRAGS 0x1 +#define V_CPL_TLS_TX_SCMD_FMT_MOREFRAGS(x) \ + ((x) << S_CPL_TLS_TX_SCMD_FMT_MOREFRAGS) +#define G_CPL_TLS_TX_SCMD_FMT_MOREFRAGS(x) \ + (((x) >> S_CPL_TLS_TX_SCMD_FMT_MOREFRAGS) & \ + M_CPL_TLS_TX_SCMD_FMT_MOREFRAGS) +#define F_CPL_TLS_TX_SCMD_FMT_MOREFRAGS V_CPL_TLS_TX_SCMD_FMT_MOREFRAGS(1U) + +#define S_CPL_TLS_TX_SCMD_FMT_LASTFRAGS 19 +#define M_CPL_TLS_TX_SCMD_FMT_LASTFRAGS 0x1 +#define V_CPL_TLS_TX_SCMD_FMT_LASTFRAGS(x) \ + ((x) << S_CPL_TLS_TX_SCMD_FMT_LASTFRAGS) +#define G_CPL_TLS_TX_SCMD_FMT_LASTFRAGS(x) \ + (((x) >> S_CPL_TLS_TX_SCMD_FMT_LASTFRAGS) & \ + M_CPL_TLS_TX_SCMD_FMT_LASTFRAGS) +#define F_CPL_TLS_TX_SCMD_FMT_LASTFRAGS V_CPL_TLS_TX_SCMD_FMT_LASTFRAGS(1U) + +#define S_CPL_TLS_TX_SCMD_FMT_TLSCOMPPDU 18 +#define M_CPL_TLS_TX_SCMD_FMT_TLSCOMPPDU 0x1 +#define V_CPL_TLS_TX_SCMD_FMT_TLSCOMPPDU(x) \ + ((x) << S_CPL_TLS_TX_SCMD_FMT_TLSCOMPPDU) +#define G_CPL_TLS_TX_SCMD_FMT_TLSCOMPPDU(x) \ + (((x) >> S_CPL_TLS_TX_SCMD_FMT_TLSCOMPPDU) & \ + M_CPL_TLS_TX_SCMD_FMT_TLSCOMPPDU) +#define F_CPL_TLS_TX_SCMD_FMT_TLSCOMPPDU V_CPL_TLS_TX_SCMD_FMT_TLSCOMPPDU(1U) + +#define S_CPL_TLS_TX_SCMD_FMT_PAYLOADONLY 17 +#define M_CPL_TLS_TX_SCMD_FMT_PAYLOADONLY 0x1 +#define V_CPL_TLS_TX_SCMD_FMT_PAYLOADONLY(x) \ + ((x) << S_CPL_TLS_TX_SCMD_FMT_PAYLOADONLY) +#define G_CPL_TLS_TX_SCMD_FMT_PAYLOADONLY(x) \ + (((x) >> S_CPL_TLS_TX_SCMD_FMT_PAYLOADONLY) & \ + M_CPL_TLS_TX_SCMD_FMT_PAYLOADONLY) +#define F_CPL_TLS_TX_SCMD_FMT_PAYLOADONLY \ + V_CPL_TLS_TX_SCMD_FMT_PAYLOADONLY(1U) + +#define S_CPL_TLS_TX_SCMD_FMT_TLSFRAGENABLE 16 +#define M_CPL_TLS_TX_SCMD_FMT_TLSFRAGENABLE 0x1 +#define V_CPL_TLS_TX_SCMD_FMT_TLSFRAGENABLE(x) \ + ((x) << S_CPL_TLS_TX_SCMD_FMT_TLSFRAGENABLE) +#define G_CPL_TLS_TX_SCMD_FMT_TLSFRAGENABLE(x) \ + (((x) >> S_CPL_TLS_TX_SCMD_FMT_TLSFRAGENABLE) & \ + M_CPL_TLS_TX_SCMD_FMT_TLSFRAGENABLE) +#define F_CPL_TLS_TX_SCMD_FMT_TLSFRAGENABLE \ + V_CPL_TLS_TX_SCMD_FMT_TLSFRAGENABLE(1U) + +#define S_CPL_TLS_TX_SCMD_FMT_MACONLY 15 +#define M_CPL_TLS_TX_SCMD_FMT_MACONLY 0x1 +#define V_CPL_TLS_TX_SCMD_FMT_MACONLY(x) \ + ((x) << S_CPL_TLS_TX_SCMD_FMT_MACONLY) +#define G_CPL_TLS_TX_SCMD_FMT_MACONLY(x) \ + (((x) >> S_CPL_TLS_TX_SCMD_FMT_MACONLY) & M_CPL_TLS_TX_SCMD_FMT_MACONLY) +#define F_CPL_TLS_TX_SCMD_FMT_MACONLY V_CPL_TLS_TX_SCMD_FMT_MACONLY(1U) + +#define S_CPL_TLS_TX_SCMD_FMT_AADIVDROP 14 +#define M_CPL_TLS_TX_SCMD_FMT_AADIVDROP 0x1 +#define V_CPL_TLS_TX_SCMD_FMT_AADIVDROP(x) \ + ((x) << S_CPL_TLS_TX_SCMD_FMT_AADIVDROP) +#define G_CPL_TLS_TX_SCMD_FMT_AADIVDROP(x) \ + (((x) >> S_CPL_TLS_TX_SCMD_FMT_AADIVDROP) & \ + M_CPL_TLS_TX_SCMD_FMT_AADIVDROP) +#define F_CPL_TLS_TX_SCMD_FMT_AADIVDROP V_CPL_TLS_TX_SCMD_FMT_AADIVDROP(1U) + +#define S_CPL_TLS_TX_SCMD_FMT_HDRLENGTH 0 +#define M_CPL_TLS_TX_SCMD_FMT_HDRLENGTH 0x3fff +#define V_CPL_TLS_TX_SCMD_FMT_HDRLENGTH(x) \ + ((x) << S_CPL_TLS_TX_SCMD_FMT_HDRLENGTH) +#define G_CPL_TLS_TX_SCMD_FMT_HDRLENGTH(x) \ + (((x) >> S_CPL_TLS_TX_SCMD_FMT_HDRLENGTH) & \ + M_CPL_TLS_TX_SCMD_FMT_HDRLENGTH) + struct cpl_rcb_upd { __be32 op_to_tid; __be32 opcode_psn; __u8 nodata_to_cnprepclr; - __u8 r0; + __u8 rsp_nak_seqclr_pkd; __be16 wrptr; __be32 length; }; @@ -6202,13 +6614,6 @@ struct cpl_roce_cqe { #define G_CPL_ROCE_CQE_QPID(x) \ (((x) >> S_CPL_ROCE_CQE_QPID) & M_CPL_ROCE_CQE_QPID) -#define S_CPL_ROCE_CQE_EXTMODE 11 -#define M_CPL_ROCE_CQE_EXTMODE 0x1 -#define V_CPL_ROCE_CQE_EXTMODE(x) ((x) << S_CPL_ROCE_CQE_EXTMODE) -#define G_CPL_ROCE_CQE_EXTMODE(x) \ - (((x) >> S_CPL_ROCE_CQE_EXTMODE) & M_CPL_ROCE_CQE_EXTMODE) -#define F_CPL_ROCE_CQE_EXTMODE V_CPL_ROCE_CQE_EXTMODE(1U) - #define S_CPL_ROCE_CQE_GENERATION_BIT 10 #define M_CPL_ROCE_CQE_GENERATION_BIT 0x1 #define V_CPL_ROCE_CQE_GENERATION_BIT(x) \ @@ -6249,6 +6654,13 @@ struct cpl_roce_cqe { #define G_CPL_ROCE_CQE_WR_TYPE_EXT(x) \ (((x) >> S_CPL_ROCE_CQE_WR_TYPE_EXT) & M_CPL_ROCE_CQE_WR_TYPE_EXT) +#define S_CPL_ROCE_CQE_EXTMODE 23 +#define M_CPL_ROCE_CQE_EXTMODE 0x1 +#define V_CPL_ROCE_CQE_EXTMODE(x) ((x) << S_CPL_ROCE_CQE_EXTMODE) +#define G_CPL_ROCE_CQE_EXTMODE(x) \ + (((x) >> S_CPL_ROCE_CQE_EXTMODE) & M_CPL_ROCE_CQE_EXTMODE) +#define F_CPL_ROCE_CQE_EXTMODE V_CPL_ROCE_CQE_EXTMODE(1U) + #define S_CPL_ROCE_CQE_SRQ 0 #define M_CPL_ROCE_CQE_SRQ 0xfff #define V_CPL_ROCE_CQE_SRQ(x) ((x) << S_CPL_ROCE_CQE_SRQ) @@ -6304,13 +6716,6 @@ struct cpl_roce_cqe_fw { #define G_CPL_ROCE_CQE_FW_QPID(x) \ (((x) >> S_CPL_ROCE_CQE_FW_QPID) & M_CPL_ROCE_CQE_FW_QPID) -#define S_CPL_ROCE_CQE_FW_EXTMODE 11 -#define M_CPL_ROCE_CQE_FW_EXTMODE 0x1 -#define V_CPL_ROCE_CQE_FW_EXTMODE(x) ((x) << S_CPL_ROCE_CQE_FW_EXTMODE) -#define G_CPL_ROCE_CQE_FW_EXTMODE(x) \ - (((x) >> S_CPL_ROCE_CQE_FW_EXTMODE) & M_CPL_ROCE_CQE_FW_EXTMODE) -#define F_CPL_ROCE_CQE_FW_EXTMODE V_CPL_ROCE_CQE_FW_EXTMODE(1U) - #define S_CPL_ROCE_CQE_FW_GENERATION_BIT 10 #define M_CPL_ROCE_CQE_FW_GENERATION_BIT 0x1 #define V_CPL_ROCE_CQE_FW_GENERATION_BIT(x) \ @@ -6353,6 +6758,14 @@ struct cpl_roce_cqe_fw { #define G_CPL_ROCE_CQE_FW_WR_TYPE_EXT(x) \ (((x) >> S_CPL_ROCE_CQE_FW_WR_TYPE_EXT) & M_CPL_ROCE_CQE_FW_WR_TYPE_EXT) +#define S_CPL_ROCE_CQE_FW_EXTMODE 23 +#define M_CPL_ROCE_CQE_FW_EXTMODE 0x1 +#define V_CPL_ROCE_CQE_FW_EXTMODE(x) ((x) << S_CPL_ROCE_CQE_FW_EXTMODE) +#define G_CPL_ROCE_CQE_FW_EXTMODE(x) \ + (((x) >> S_CPL_ROCE_CQE_FW_EXTMODE) & M_CPL_ROCE_CQE_FW_EXTMODE) +#define F_CPL_ROCE_CQE_FW_EXTMODE V_CPL_ROCE_CQE_FW_EXTMODE(1U) + + #define S_CPL_ROCE_CQE_FW_SRQ 0 #define M_CPL_ROCE_CQE_FW_SRQ 0xfff #define V_CPL_ROCE_CQE_FW_SRQ(x) ((x) << S_CPL_ROCE_CQE_FW_SRQ) @@ -6360,16 +6773,16 @@ struct cpl_roce_cqe_fw { (((x) >> S_CPL_ROCE_CQE_FW_SRQ) & M_CPL_ROCE_CQE_FW_SRQ) struct cpl_roce_cqe_err { - __be32 op_to_CQID; - __be32 Tid_FlitCnt; - __be32 QPID_to_WR_type; - __be32 Length; - __be32 TAG; - __be32 MSN; - __be32 SE_to_SRQ; - __be32 RQE; - __be32 ExtInfoMS[2]; - __be32 ExtInfoLS[2]; + __be32 op_to_cqid; + __be32 tid_flitcnt; + __be32 qpid_to_wr_type; + __be32 length; + __be32 tag; + __be32 msn; + __be32 se_to_srq; + __be32 rqe; + __be32 extinfoms[2]; + __be32 extinfols[2]; }; #define S_CPL_ROCE_CQE_ERR_OPCODE 24 @@ -6408,13 +6821,6 @@ struct cpl_roce_cqe_err { #define G_CPL_ROCE_CQE_ERR_QPID(x) \ (((x) >> S_CPL_ROCE_CQE_ERR_QPID) & M_CPL_ROCE_CQE_ERR_QPID) -#define S_CPL_ROCE_CQE_ERR_EXTMODE 11 -#define M_CPL_ROCE_CQE_ERR_EXTMODE 0x1 -#define V_CPL_ROCE_CQE_ERR_EXTMODE(x) ((x) << S_CPL_ROCE_CQE_ERR_EXTMODE) -#define G_CPL_ROCE_CQE_ERR_EXTMODE(x) \ - (((x) >> S_CPL_ROCE_CQE_ERR_EXTMODE) & M_CPL_ROCE_CQE_ERR_EXTMODE) -#define F_CPL_ROCE_CQE_ERR_EXTMODE V_CPL_ROCE_CQE_ERR_EXTMODE(1U) - #define S_CPL_ROCE_CQE_ERR_GENERATION_BIT 10 #define M_CPL_ROCE_CQE_ERR_GENERATION_BIT 0x1 #define V_CPL_ROCE_CQE_ERR_GENERATION_BIT(x) \ @@ -6458,6 +6864,14 @@ struct cpl_roce_cqe_err { #define G_CPL_ROCE_CQE_ERR_WR_TYPE_EXT(x) \ *** 380 LINES SKIPPED ***