Date: Sun, 14 Dec 2014 17:38:44 +0000 (UTC) From: Andrew Turner <andrew@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-10@freebsd.org Subject: svn commit: r275770 - stable/10/contrib/binutils/gas/config Message-ID: <201412141738.sBEHciRH000923@svn.freebsd.org>
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Author: andrew Date: Sun Dec 14 17:38:43 2014 New Revision: 275770 URL: https://svnweb.freebsd.org/changeset/base/275770 Log: MFC 275415: Allow the UAL APSR_nzcv format for the mrc and mrc2 instructions. The clang integrated assembler only allows these forms so binutils will need to support them. Sponsored by: ABT Systems Ltd MFC 275584: Fix mrc and mrc2 with APSR_nzcv. Binutils encodes it internally as 0 where we need it to be set to 15 for it to be equivalent to r15. Sponsored by: ABT Systems Ltd Modified: stable/10/contrib/binutils/gas/config/tc-arm.c Directory Properties: stable/10/ (props changed) Modified: stable/10/contrib/binutils/gas/config/tc-arm.c ============================================================================== --- stable/10/contrib/binutils/gas/config/tc-arm.c Sun Dec 14 17:28:02 2014 (r275769) +++ stable/10/contrib/binutils/gas/config/tc-arm.c Sun Dec 14 17:38:43 2014 (r275770) @@ -6771,7 +6771,11 @@ do_co_reg (void) { inst.instruction |= inst.operands[0].reg << 8; inst.instruction |= inst.operands[1].imm << 21; - inst.instruction |= inst.operands[2].reg << 12; + /* If this is a vector we are using the APSR_nzcv syntax, encode as r15 */ + if (inst.operands[2].isvec != 0) + inst.instruction |= 15 << 12; + else + inst.instruction |= inst.operands[2].reg << 12; inst.instruction |= inst.operands[3].reg << 16; inst.instruction |= inst.operands[4].reg; inst.instruction |= inst.operands[5].imm << 5; @@ -15029,7 +15033,7 @@ static const struct asm_opcode insns[] = TCE(stc, c000000, ec000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), TC3(stcl, c400000, ec400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), TCE(mcr, e000010, ee000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), - TCE(mrc, e100010, ee100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), + TCE(mrc, e100010, ee100010, 6, (RCP, I7b, APSR_RR, RCN, RCN, oI7b), co_reg, co_reg), #undef ARM_VARIANT #define ARM_VARIANT &arm_ext_v2s /* ARM 3 - swp instructions. */ @@ -15088,7 +15092,7 @@ static const struct asm_opcode insns[] = TUF(stc2l, c400000, fc400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), TUF(cdp2, e000000, fe000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp), TUF(mcr2, e000010, fe000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), - TUF(mrc2, e100010, fe100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), + TUF(mrc2, e100010, fe100010, 6, (RCP, I7b, APSR_RR, RCN, RCN, oI7b), co_reg, co_reg), #undef ARM_VARIANT #define ARM_VARIANT &arm_ext_v5exp /* ARM Architecture 5TExP. */
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