From owner-svn-src-head@freebsd.org Wed Sep 21 05:33:20 2016 Return-Path: Delivered-To: svn-src-head@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 40A8FBE38C2; Wed, 21 Sep 2016 05:33:20 +0000 (UTC) (envelope-from wma@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id E379B3A7; Wed, 21 Sep 2016 05:33:19 +0000 (UTC) (envelope-from wma@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id u8L5XJ7f086851; Wed, 21 Sep 2016 05:33:19 GMT (envelope-from wma@FreeBSD.org) Received: (from wma@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id u8L5XJgr086850; Wed, 21 Sep 2016 05:33:19 GMT (envelope-from wma@FreeBSD.org) Message-Id: <201609210533.u8L5XJgr086850@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: wma set sender to wma@FreeBSD.org using -f From: Wojciech Macek Date: Wed, 21 Sep 2016 05:33:19 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r306070 - head/sys/arm/arm X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 21 Sep 2016 05:33:20 -0000 Author: wma Date: Wed Sep 21 05:33:18 2016 New Revision: 306070 URL: https://svnweb.freebsd.org/changeset/base/306070 Log: Add support for SPI-mapped MSI interrupts outside of GICv2m. SPI-mapped MSI interrupts coming from a controller other than GICv2m need to have their trigger and polarity properly configured. This patch fixes MSI/MSI-X on Annapurna Alpine platform with GICv2. Obtained from: Semihalf Submitted by: Michal Stanek Sponsored by: Annapurna Labs Reviewed by: skra, wma Differential Revision: https://reviews.freebsd.org/D7698 Modified: head/sys/arm/arm/gic.c Modified: head/sys/arm/arm/gic.c ============================================================================== --- head/sys/arm/arm/gic.c Wed Sep 21 05:22:49 2016 (r306069) +++ head/sys/arm/arm/gic.c Wed Sep 21 05:33:18 2016 (r306070) @@ -835,6 +835,26 @@ gic_map_fdt(device_t dev, u_int ncells, #endif static int +gic_map_msi(device_t dev, struct intr_map_data_msi *msi_data, u_int *irqp, + enum intr_polarity *polp, enum intr_trigger *trigp) +{ + struct gic_irqsrc *gi; + + /* Map a non-GICv2m MSI */ + gi = (struct gic_irqsrc *)msi_data->isrc; + if (gi == NULL) + return (ENXIO); + + *irqp = gi->gi_irq; + + /* MSI/MSI-X interrupts are always edge triggered with high polarity */ + *polp = INTR_POLARITY_HIGH; + *trigp = INTR_TRIGGER_EDGE; + + return (0); +} + +static int gic_map_intr(device_t dev, struct intr_map_data *data, u_int *irqp, enum intr_polarity *polp, enum intr_trigger *trigp) { @@ -842,6 +862,7 @@ gic_map_intr(device_t dev, struct intr_m enum intr_polarity pol; enum intr_trigger trig; struct arm_gic_softc *sc; + struct intr_map_data_msi *dam; #ifdef FDT struct intr_map_data_fdt *daf; #endif @@ -860,6 +881,12 @@ gic_map_intr(device_t dev, struct intr_m __func__)); break; #endif + case INTR_MAP_DATA_MSI: + /* Non-GICv2m MSI */ + dam = (struct intr_map_data_msi *)data; + if (gic_map_msi(dev, dam, &irq, &pol, &trig) != 0) + return (EINVAL); + break; default: return (ENOTSUP); } @@ -907,6 +934,7 @@ arm_gic_setup_intr(device_t dev, struct enum intr_polarity pol; if ((gi->gi_flags & GI_FLAG_MSI) == GI_FLAG_MSI) { + /* GICv2m MSI */ pol = gi->gi_pol; trig = gi->gi_trig; KASSERT(pol == INTR_POLARITY_HIGH,