From owner-freebsd-hackers Wed Jun 7 17:28:42 1995 Return-Path: hackers-owner Received: (from majordom@localhost) by freefall.cdrom.com (8.6.10/8.6.6) id RAA24525 for hackers-outgoing; Wed, 7 Jun 1995 17:28:42 -0700 Received: from cs.weber.edu (cs.weber.edu [137.190.16.16]) by freefall.cdrom.com (8.6.10/8.6.6) with SMTP id RAA24497 ; Wed, 7 Jun 1995 17:27:12 -0700 Received: by cs.weber.edu (4.1/SMI-4.1.1) id AA07812; Wed, 7 Jun 95 18:19:01 MDT From: terry@cs.weber.edu (Terry Lambert) Message-Id: <9506080019.AA07812@cs.weber.edu> Subject: Re: 2.0.5-A: Very disheartening? To: phk@ref.tfs.com (Poul-Henning Kamp) Date: Wed, 7 Jun 95 18:19:01 MDT Cc: uhclem%nemesis@fw.ast.com, jgreco@brasil.moneng.mei.com, hackers@FreeBSD.org, bugs@FreeBSD.org In-Reply-To: <199506072203.PAA03872@ref.tfs.com> from "Poul-Henning Kamp" at Jun 7, 95 03:03:30 pm X-Mailer: ELM [version 2.4dev PL52] Sender: hackers-owner@FreeBSD.org Precedence: bulk > > > As far as I can see, the only failing part is the mechanisms associated > > > with a compressed kernel, or the compressed kernel itself and certain > > > types of cache subsystems. I can boot from a floppy with a uncompressed > > > kernel and that works fine too. Only the compressed kernel has trouble. > > > > This makes sense, actually. > > Explain please... Split I and D would cause this. Also, second reference cached code (uncompressed would be first reference, so the cache would be clean) on systems with broken caches. Even on working caches, you'd probably want to either set the pages you are loading the compressed image into non-cacheable, or BINVD the target pages from the compression to insure that you don't have bad code in your cache. The instruction prefetch crap, and the undocumented-but-existing cache crap is described in detail in "The Undocumented PC" (one of my favorite PC computer reference works). More general code that world detect cache writeback failure and other issues would be a good thing, but would probably mean two-staging the boot to make it happy. It could certainly be useful for HiNT chipset NiCE EISA motherboards and other boards that lie about cache writeback. The instruction prefetch cache issue should be an easy one to test for... are any of the following true: o All failures of this type have been on Pentium boxes o All failures of this type have been on non-Pentium boxes If the latter, it's instruction prefetch cache flushing that's needed. If the former, it's another issue. Terry Lambert terry@cs.weber.edu --- Any opinions in this posting are my own and not those of my present or previous employers.