Date: Thu, 15 Aug 2013 13:50:24 -0300 From: Luiz Otavio O Souza <loos.br@gmail.com> To: freebsd-arm@freebsd.org Subject: i2c driver for RPi Message-ID: <DDB4F427-6E22-434E-9532-7BD7289F3AD0@gmail.com>
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--Apple-Mail-42-993749787 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=us-ascii Hello guys, I've written the I2C (BSC - broadcom serial controller) driver for RPi. The test was done by reading the registers of two lm75 on the same I2C = bus (the only one available on my RPi). You have to manually switch the I2C pins to alt0 function. There are two = bsc controllers on SoC, the older ones uses the bsc0 and gpio pins 0 and = 1 while the newer boards uses the bsc1 with gpio pins 2 and 3. There is a third bsc controller which is used for the HDMI connection. I = have not touched this one (although it should just work). So for my basics tests, here is what i did: root@raspberry-pi:~ # sysctl dev.gpio.0.pin.0.function=3Dalt0 dev.gpio.0.pin.0.function: input -> alt0 root@raspberry-pi:~ # sysctl dev.gpio.0.pin.1.function=3Dalt0 dev.gpio.0.pin.1.function: input -> alt0 root@raspberry-pi:~ # cd src/lm75 root@raspberry-pi:~/src/lm75 # ./lm75 -d 150 -f /dev/iic0 -a lm75 in comparator mode O.S. polarity: active low Fault Queue: 1 temperature: 17.0C o.s. temperature: 80.0C hyst temperature: 75.0C root@raspberry-pi:~/src/lm75 # ./lm75 -d 158 -f /dev/iic0 -a lm75 in comparator mode O.S. polarity: active low Fault Queue: 1 temperature: 16.5C o.s. temperature: 80.0C hyst temperature: 75.0C The lm75 code is at: http://loos.no-ip.org/lm75.tar.gz The BSC driver also exports some knobs under the dev.bsc sysctl: root@raspberry-pi:~/src/lm75 # sysctl dev.bsc.0 dev.bsc.0.%desc: BCM2708/2835 BSC controller dev.bsc.0.%driver: bsc dev.bsc.0.%parent: simplebus0 dev.bsc.0.clock: 100000 dev.bsc.0.clock_stretch: 64 dev.bsc.0.fall_edge_delay: 48 dev.bsc.0.rise_edge_delay: 48 And the dmesg (for bsc part): bsc0: <BCM2708/2835 BSC controller> mem 0x20205000-0x2020501f irq 61 on = simplebus0 iicbus0: <Philips I2C bus> on bsc0 iic0: <I2C generic I/O> on iicbus0 bsc1: <BCM2708/2835 BSC controller> mem 0x20804000-0x2080401f irq 61 on = simplebus0 iicbus1: <Philips I2C bus> on bsc1 iic1: <I2C generic I/O> on iicbus1 Is this ok ? Thanks, Luiz --Apple-Mail-42-993749787 Content-Disposition: attachment; filename=bcm2835_bsc.diff Content-Type: application/octet-stream; name="bcm2835_bsc.diff" Content-Transfer-Encoding: 7bit Index: sys/arm/broadcom/bcm2835/files.bcm2835 =================================================================== --- sys/arm/broadcom/bcm2835/files.bcm2835 (revision 254251) +++ sys/arm/broadcom/bcm2835/files.bcm2835 (working copy) @@ -1,5 +1,6 @@ # $FreeBSD$ +arm/broadcom/bcm2835/bcm2835_bsc.c optional bcm2835_bsc arm/broadcom/bcm2835/bcm2835_dma.c standard arm/broadcom/bcm2835/bcm2835_fb.c optional sc arm/broadcom/bcm2835/bcm2835_gpio.c optional gpio Index: sys/arm/conf/RPI-B =================================================================== --- sys/arm/conf/RPI-B (revision 254251) +++ sys/arm/conf/RPI-B (working copy) @@ -79,6 +79,11 @@ device gpio device gpioled +# I2C +device iic +device iicbus +device bcm2835_bsc + options KDB options DDB #Enable the kernel debugger options INVARIANTS #Enable calls of extra sanity checking Index: sys/boot/fdt/dts/bcm2835.dtsi =================================================================== --- sys/boot/fdt/dts/bcm2835.dtsi (revision 254251) +++ sys/boot/fdt/dts/bcm2835.dtsi (working copy) @@ -396,6 +396,22 @@ }; }; + bsc0 { + compatible = "broadcom,bcm2835-bsc", + "broadcom,bcm2708-bsc"; + reg = <0x205000 0x20>; + interrupts = <61>; + interrupt-parent = <&intc>; + }; + + bsc1 { + compatible = "broadcom,bcm2835-bsc", + "broadcom,bcm2708-bsc"; + reg = <0x804000 0x20>; + interrupts = <61>; + interrupt-parent = <&intc>; + }; + dma: dma { compatible = "broadcom,bcm2835-dma", "broadcom,bcm2708-dma"; --- /dev/null 2013-08-15 12:00:00.000000000 -0300 +++ sys/arm/broadcom/bcm2835/bcm2835_bsc.c 2013-08-15 12:02:01.400235929 -0300 @@ -0,0 +1,504 @@ +/*- + * Copyright (c) 2001 Tsubai Masanari. + * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org> + * Copyright (c) 2013 Luiz Otavio O Souza <loos@freebsd.org> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + */ +#include <sys/cdefs.h> +__FBSDID("$FreeBSD$"); + +#include <sys/param.h> +#include <sys/systm.h> +#include <sys/kernel.h> +#include <sys/lock.h> +#include <sys/module.h> +#include <sys/mutex.h> +#include <sys/bus.h> +#include <machine/resource.h> +#include <machine/bus.h> +#include <sys/rman.h> +#include <sys/sysctl.h> + +#include <dev/iicbus/iicbus.h> +#include <dev/iicbus/iiconf.h> +#include <dev/ofw/ofw_bus.h> +#include <dev/ofw/ofw_bus_subr.h> +#include "iicbus_if.h" + +struct bcm_bsc_softc { + device_t sc_dev; + struct mtx sc_mtx; + struct resource * sc_mem_res; + struct resource * sc_irq_res; + bus_space_tag_t sc_bst; + bus_space_handle_t sc_bsh; + phandle_t sc_node; + uint16_t sc_resid; + uint8_t *sc_data; + void * sc_intrhand; + int sc_flags; +}; + +#define BCM_BSC_CTRL 0x00 +#define BCM_BSC_CTRL_I2CEN (1 << 15) +#define BCM_BSC_CTRL_INTR (1 << 10) +#define BCM_BSC_CTRL_INTT (1 << 9) +#define BCM_BSC_CTRL_INTD (1 << 8) +#define BCM_BSC_CTRL_ST (1 << 7) +#define BCM_BSC_CTRL_CLEAR1 (1 << 5) +#define BCM_BSC_CTRL_CLEAR0 (1 << 4) +#define BCM_BSC_CTRL_READ (1 << 0) +#define BCM_BSC_STATUS 0x04 +#define BCM_BSC_STATUS_CLKT (1 << 9) +#define BCM_BSC_STATUS_ERR (1 << 8) +#define BCM_BSC_STATUS_RXF (1 << 7) +#define BCM_BSC_STATUS_TXE (1 << 6) +#define BCM_BSC_STATUS_RXD (1 << 5) +#define BCM_BSC_STATUS_TXD (1 << 4) +#define BCM_BSC_STATUS_RXR (1 << 3) +#define BCM_BSC_STATUS_TXW (1 << 2) +#define BCM_BSC_STATUS_DONE (1 << 1) +#define BCM_BSC_STATUS_TA (1 << 0) +#define BCM_BSC_DLEN 0x08 +#define BCM_BSC_SLAVE 0x0c +#define BCM_BSC_DATA 0x10 +#define BCM_BSC_CLOCK 0x14 +#define BCM_BSC_DELAY 0x18 +#define BCM_BSC_CLKT 0x1c + +#define I2C_BUSY 0x01 +#define I2C_READ 0x02 +#define I2C_ERROR 0x04 + +#define BCM_BSC_WRITE(_sc, _off, _val) \ + bus_space_write_4(_sc->sc_bst, _sc->sc_bsh, _off, _val) +#define BCM_BSC_READ(_sc, _off) \ + bus_space_read_4(_sc->sc_bst, _sc->sc_bsh, _off) + +#define BCM_BSC_LOCK(_sc) \ + mtx_lock(&(_sc)->sc_mtx) +#define BCM_BSC_UNLOCK(_sc) \ + mtx_unlock(&(_sc)->sc_mtx) + +static void bcm_bsc_intr(void *); + +static void +bcm_bsc_modifyreg(struct bcm_bsc_softc *sc, uint32_t off, uint32_t mask, + uint32_t value) +{ + uint32_t reg; + + reg = BCM_BSC_READ(sc, off); + reg &= ~mask; + reg |= value; + BCM_BSC_WRITE(sc, off, reg); +} + +static int +bcm_bsc_clock_proc(SYSCTL_HANDLER_ARGS) +{ + struct bcm_bsc_softc *sc; + uint32_t clk; + int error; + + sc = (struct bcm_bsc_softc *)arg1; + + clk = BCM_BSC_READ(sc, BCM_BSC_CLOCK); + if (clk == 0) + clk = 32768; + clk = 150000000UL / clk; + error = sysctl_handle_int(oidp, &clk, sizeof(clk), req); + if (error != 0 || req->newptr == NULL) + return (error); + + BCM_BSC_LOCK(sc); + clk = 150000000UL / clk; + if (clk > 0xffff) + clk = 0xffff; + BCM_BSC_WRITE(sc, BCM_BSC_CLOCK, clk); + BCM_BSC_UNLOCK(sc); + + return (0); +} + +static int +bcm_bsc_clkt_proc(SYSCTL_HANDLER_ARGS) +{ + struct bcm_bsc_softc *sc; + uint32_t clkt; + int error; + + sc = (struct bcm_bsc_softc *)arg1; + + clkt = BCM_BSC_READ(sc, BCM_BSC_CLKT); + error = sysctl_handle_int(oidp, &clkt, sizeof(clkt), req); + if (error != 0 || req->newptr == NULL) + return (error); + + BCM_BSC_LOCK(sc); + BCM_BSC_WRITE(sc, BCM_BSC_CLKT, clkt); + BCM_BSC_UNLOCK(sc); + return (0); +} + +static int +bcm_bsc_fall_proc(SYSCTL_HANDLER_ARGS) +{ + struct bcm_bsc_softc *sc; + uint32_t clk, reg; + int error; + + sc = (struct bcm_bsc_softc *)arg1; + + reg = BCM_BSC_READ(sc, BCM_BSC_DELAY); + reg >>= 16; + error = sysctl_handle_int(oidp, ®, sizeof(reg), req); + if (error != 0 || req->newptr == NULL) + return (error); + + BCM_BSC_LOCK(sc); + clk = BCM_BSC_READ(sc, BCM_BSC_CLOCK); + clk = 150000000UL / clk; + if (reg > clk / 2) + reg = clk / 2 - 1; + bcm_bsc_modifyreg(sc, BCM_BSC_DELAY, 0xffff0000, reg << 16); + BCM_BSC_UNLOCK(sc); + return (0); +} + +static int +bcm_bsc_rise_proc(SYSCTL_HANDLER_ARGS) +{ + struct bcm_bsc_softc *sc; + uint32_t clk, reg; + int error; + + sc = (struct bcm_bsc_softc *)arg1; + + reg = BCM_BSC_READ(sc, BCM_BSC_DELAY); + reg &= 0xffff; + error = sysctl_handle_int(oidp, ®, sizeof(reg), req); + if (error != 0 || req->newptr == NULL) + return (error); + + BCM_BSC_LOCK(sc); + clk = BCM_BSC_READ(sc, BCM_BSC_CLOCK); + clk = 150000000UL / clk; + if (reg > clk / 2) + reg = clk / 2 - 1; + bcm_bsc_modifyreg(sc, BCM_BSC_DELAY, 0xffff, reg); + BCM_BSC_UNLOCK(sc); + return (0); +} + +static void +bcm_bsc_sysctl_init(struct bcm_bsc_softc *sc) +{ + struct sysctl_ctx_list *ctx; + struct sysctl_oid *tree_node; + struct sysctl_oid_list *tree; + + /* + * Add system sysctl tree/handlers. + */ + ctx = device_get_sysctl_ctx(sc->sc_dev); + tree_node = device_get_sysctl_tree(sc->sc_dev); + tree = SYSCTL_CHILDREN(tree_node); + SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "clock", + CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc), + bcm_bsc_clock_proc, "IU", "I2C BUS clock frequency"); + SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "clock_stretch", + CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc), + bcm_bsc_clkt_proc, "IU", "I2C BUS clock stretch timeout"); + SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "fall_edge_delay", + CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc), + bcm_bsc_fall_proc, "IU", "I2C BUS falling edge delay"); + SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "rise_edge_delay", + CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc), + bcm_bsc_rise_proc, "IU", "I2C BUS rising edge delay"); +} + +static void +bcm_bsc_reset(struct bcm_bsc_softc *sc) +{ + + /* Clear pending interrupts. */ + BCM_BSC_WRITE(sc, BCM_BSC_STATUS, BCM_BSC_STATUS_CLKT | + BCM_BSC_STATUS_ERR | BCM_BSC_STATUS_DONE); + /* Clear the FIFO. */ + bcm_bsc_modifyreg(sc, BCM_BSC_CTRL, BCM_BSC_CTRL_CLEAR0, + BCM_BSC_CTRL_CLEAR0); +} + +static int +bcm_bsc_probe(device_t dev) +{ + + if (!ofw_bus_is_compatible(dev, "broadcom,bcm2835-bsc")) + return (ENXIO); + + device_set_desc(dev, "BCM2708/2835 BSC controller"); + return (BUS_PROBE_DEFAULT); +} + +static int +bcm_bsc_attach(device_t dev) +{ + struct bcm_bsc_softc *sc; + int rid; + + sc = device_get_softc(dev); + sc->sc_dev = dev; + + sc->sc_node = ofw_bus_get_node(dev); + if (sc->sc_node == 0 || sc->sc_node == -1) + return (EINVAL); + + rid = 0; + sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, + RF_ACTIVE); + if (!sc->sc_mem_res) { + device_printf(dev, "cannot allocate memory window\n"); + return (ENXIO); + } + + sc->sc_bst = rman_get_bustag(sc->sc_mem_res); + sc->sc_bsh = rman_get_bushandle(sc->sc_mem_res); + + rid = 0; + sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, + RF_ACTIVE | RF_SHAREABLE); + if (!sc->sc_irq_res) { + bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); + device_printf(dev, "cannot allocate interrupt\n"); + return (ENXIO); + } + + /* Hook up our interrupt handler. */ + if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE, + NULL, bcm_bsc_intr, sc, &sc->sc_intrhand)) { + bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); + bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); + device_printf(dev, "cannot setup the interrupt handler\n"); + return (ENXIO); + } + + mtx_init(&sc->sc_mtx, "bcm_bsc", NULL, MTX_DEF); + + bcm_bsc_sysctl_init(sc); + + /* Enable the BSC controller. Flush the FIFO. */ + BCM_BSC_WRITE(sc, BCM_BSC_CTRL, BCM_BSC_CTRL_I2CEN); + bcm_bsc_reset(sc); + + device_add_child(dev, "iicbus", -1); + return (bus_generic_attach(dev)); +} + +static int +bcm_bsc_detach(device_t dev) +{ + struct bcm_bsc_softc *sc; + + bus_generic_detach(dev); + + sc = device_get_softc(dev); + mtx_destroy(&sc->sc_mtx); + if (sc->sc_intrhand) + bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intrhand); + if (sc->sc_irq_res) + bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); + if (sc->sc_mem_res) + bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); + return (0); +} + +static void +bcm_bsc_intr(void *arg) +{ + struct bcm_bsc_softc *sc; + uint32_t status; + + sc = (struct bcm_bsc_softc *)arg; + + BCM_BSC_LOCK(sc); + + /* The I2C interrupt is shared among all the BSC controllers. */ + if ((sc->sc_flags & I2C_BUSY) == 0) { + BCM_BSC_UNLOCK(sc); + return; + } + + status = BCM_BSC_READ(sc, BCM_BSC_STATUS); + + /* Check for errors. */ + if (status & (BCM_BSC_STATUS_CLKT | BCM_BSC_STATUS_ERR)) { + /* Disable interrupts. */ + BCM_BSC_WRITE(sc, BCM_BSC_CTRL, BCM_BSC_CTRL_I2CEN); + sc->sc_flags |= I2C_ERROR; + bcm_bsc_reset(sc); + wakeup(sc->sc_dev); + BCM_BSC_UNLOCK(sc); + return; + } + + if (sc->sc_flags & I2C_READ) { + while (sc->sc_resid > 0 && (status & BCM_BSC_STATUS_RXD)) { + *sc->sc_data++ = BCM_BSC_READ(sc, BCM_BSC_DATA); + sc->sc_resid--; + status = BCM_BSC_READ(sc, BCM_BSC_STATUS); + } + } else { + while (sc->sc_resid > 0 && (status & BCM_BSC_STATUS_TXD)) { + BCM_BSC_WRITE(sc, BCM_BSC_DATA, *sc->sc_data++); + sc->sc_resid--; + status = BCM_BSC_READ(sc, BCM_BSC_STATUS); + } + } + + if (status & BCM_BSC_STATUS_DONE) { + /* Disable interrupts. */ + BCM_BSC_WRITE(sc, BCM_BSC_CTRL, BCM_BSC_CTRL_I2CEN); + bcm_bsc_reset(sc); + wakeup(sc->sc_dev); + } + + BCM_BSC_UNLOCK(sc); +} + +static int +bcm_bsc_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs) +{ + struct bcm_bsc_softc *sc; + uint32_t intr, read, status; + int i, err; + + sc = device_get_softc(dev); + BCM_BSC_LOCK(sc); + + if (sc->sc_flags & I2C_BUSY) + mtx_sleep(dev, &sc->sc_mtx, 0, "bcm_bsc", hz); + + if (sc->sc_flags & I2C_BUSY) { + BCM_BSC_UNLOCK(sc); + return (ETIMEDOUT); + } + + sc->sc_flags = I2C_BUSY; + + /* Clear the FIFO and the pending interrupts. */ + bcm_bsc_reset(sc); + + err = 0; + for (i = 0; i < nmsgs; i++) { + + /* Write the slave address. */ + BCM_BSC_WRITE(sc, BCM_BSC_SLAVE, (msgs[i].slave >> 1) & 0x7f); + + /* Write the data length. */ + BCM_BSC_WRITE(sc, BCM_BSC_DLEN, msgs[i].len); + + sc->sc_data = msgs[i].buf; + sc->sc_resid = msgs[i].len; + if ((msgs[i].flags & IIC_M_RD) == 0) { + /* Fill up the TX FIFO. */ + status = BCM_BSC_READ(sc, BCM_BSC_STATUS); + while (sc->sc_resid > 0 && + (status & BCM_BSC_STATUS_TXD)) { + BCM_BSC_WRITE(sc, BCM_BSC_DATA, *sc->sc_data); + sc->sc_data++; + sc->sc_resid--; + status = BCM_BSC_READ(sc, BCM_BSC_STATUS); + } + read = 0; + intr = BCM_BSC_CTRL_INTT; + sc->sc_flags &= ~I2C_READ; + } else { + sc->sc_flags |= I2C_READ; + read = BCM_BSC_CTRL_READ; + intr = BCM_BSC_CTRL_INTR; + } + intr |= BCM_BSC_CTRL_INTD; + + /* Start the transfer. */ + BCM_BSC_WRITE(sc, BCM_BSC_CTRL, BCM_BSC_CTRL_I2CEN | + BCM_BSC_CTRL_ST | read | intr); + + /* Wait for the transaction to complete. */ + err = mtx_sleep(dev, &sc->sc_mtx, 0, "bcm_bsc", hz); + + /* Check if we have a timeout or an I2C error. */ + if ((sc->sc_flags & I2C_ERROR) || err == EWOULDBLOCK) { + if (bootverbose) + device_printf(sc->sc_dev, "I2C error\n"); + err = EIO; + break; + } + } + + /* Clean the controller flags. */ + sc->sc_flags = 0; + + BCM_BSC_UNLOCK(sc); + return (err); +} + +static phandle_t +bcm_bsc_get_node(device_t bus, device_t dev) +{ + struct bcm_bsc_softc *sc; + + sc = device_get_softc(bus); + /* We only have one child, the I2C bus, which needs our own node. */ + + return (sc->sc_node); +} + +static device_method_t bcm_bsc_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, bcm_bsc_probe), + DEVMETHOD(device_attach, bcm_bsc_attach), + DEVMETHOD(device_detach, bcm_bsc_detach), + + /* iicbus interface */ + DEVMETHOD(iicbus_callback, iicbus_null_callback), + DEVMETHOD(iicbus_transfer, bcm_bsc_transfer), + + /* ofw_bus interface */ + DEVMETHOD(ofw_bus_get_node, bcm_bsc_get_node), + + DEVMETHOD_END +}; + +static devclass_t bcm_bsc_devclass; + +static driver_t bcm_bsc_driver = { + "bsc", + bcm_bsc_methods, + sizeof(struct bcm_bsc_softc), +}; + +DRIVER_MODULE(iicbus, bsc, iicbus_driver, iicbus_devclass, 0, 0); +DRIVER_MODULE(bcm2835_bsc, simplebus, bcm_bsc_driver, bcm_bsc_devclass, 0, 0); --Apple-Mail-42-993749787--
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