From owner-freebsd-mips@FreeBSD.ORG Tue Oct 4 17:52:01 2011 Return-Path: Delivered-To: freebsd-mips@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 2DC00106564A; Tue, 4 Oct 2011 17:52:01 +0000 (UTC) (envelope-from aduane@juniper.net) Received: from exprod7og101.obsmtp.com (exprod7og101.obsmtp.com [64.18.2.155]) by mx1.freebsd.org (Postfix) with ESMTP id 3D5408FC14; Tue, 4 Oct 2011 17:51:58 +0000 (UTC) Received: from P-EMHUB01-HQ.jnpr.net ([66.129.224.36]) (using TLSv1) by exprod7ob101.postini.com ([64.18.6.12]) with SMTP; Tue, 04 Oct 2011 10:52:00 PDT Received: from p-emfe02-wf.jnpr.net (172.28.145.25) by P-EMHUB01-HQ.jnpr.net (172.24.192.35) with Microsoft SMTP Server (TLS) id 8.3.83.0; Tue, 4 Oct 2011 10:49:15 -0700 Received: from EMBX01-WF.jnpr.net ([fe80::1914:3299:33d9:e43b]) by p-emfe02-wf.jnpr.net ([fe80::c126:c633:d2dc:8090%11]) with mapi; Tue, 4 Oct 2011 13:49:14 -0400 From: Andrew Duane To: Jayachandran C. Date: Tue, 4 Oct 2011 13:49:13 -0400 Thread-Topic: svn commit: r225892 - head/sys/mips/mips Thread-Index: AcyCvcF6cG9ov6qZQcG5nXLeiN6ipAAABdqw Message-ID: References: In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: en-US Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Cc: Alexander Motin , Kostik, "freebsd-mips@freebsd.org" , Belousov Subject: RE: svn commit: r225892 - head/sys/mips/mips X-BeenThere: freebsd-mips@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Porting FreeBSD to MIPS List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 04 Oct 2011 17:52:01 -0000 An assert, or some other check would work. Could you just add "EndWaitSkip = - StartWaitSkip" somehow? I just worry that some day it won't be 16 bytes a= ny more.... =A0................................... Andrew Duane Juniper Networks o=A0=A0=A0+1 978 589 0551 m=A0 +1 603-770-7088 aduane@juniper.net =A0 > -----Original Message----- > From: c.jayachandran@gmail.com [mailto:c.jayachandran@gmail.com] On > Behalf Of Jayachandran C. > Sent: Tuesday, October 04, 2011 10:48 AM > To: Andrew Duane > Cc: Warner Losh; Adrian Chadd; Kostik Belousov; Alexander Motin; > freebsd-mips@freebsd.org > Subject: Re: svn commit: r225892 - head/sys/mips/mips >=20 > On Tue, Oct 4, 2011 at 9:34 PM, Andrew Duane > wrote: > > The MIPS manual volume 3 says there is a 3 cycle "typical" wait > between an MTC0 that messes with Status[IE] and an interrupted > instruction. That hazard doesn't seem to apply here, to any of the > cases we have. > > > > I do have a question: in StartWaitSkip, the value of Status[IE] is > being toggled, not cleared. Is that correct? Do we always guarantee > that it will be set on entry here? >=20 > Interrupts have to be enabled in cpu_idle(), there is an assert in the > beginning of cpu_idle which checks this. >=20 > > I had also made a comment about the "PTR_ADDU k1, 16 =A0 =A0# skip over > wait" in MipsKernIntr; I think it would be safer (and clearer) to do > "PTR_LA =A0 =A0 =A0 =A0k1, EndWaitSkip" instead. >=20 > Loading an immediate address takes more instructions (esp in 64 bit) > adding 16 is just one instruction. I should really add an KASSERT > somewhere to make sure that EndWaitSkip - StartWaitSkip is 16... >=20 > JC.