From owner-svn-src-all@freebsd.org Wed Jun 26 01:14:41 2019 Return-Path: Delivered-To: svn-src-all@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 2626115DBEC9; Wed, 26 Jun 2019 01:14:41 +0000 (UTC) (envelope-from jhibbits@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) server-signature RSA-PSS (4096 bits) client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id BF7F586721; Wed, 26 Jun 2019 01:14:40 +0000 (UTC) (envelope-from jhibbits@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 7CC4E20799; Wed, 26 Jun 2019 01:14:40 +0000 (UTC) (envelope-from jhibbits@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id x5Q1Eeq9069257; Wed, 26 Jun 2019 01:14:40 GMT (envelope-from jhibbits@FreeBSD.org) Received: (from jhibbits@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id x5Q1Ee7e069255; Wed, 26 Jun 2019 01:14:40 GMT (envelope-from jhibbits@FreeBSD.org) Message-Id: <201906260114.x5Q1Ee7e069255@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: jhibbits set sender to jhibbits@FreeBSD.org using -f From: Justin Hibbits Date: Wed, 26 Jun 2019 01:14:40 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r349402 - in head/sys/powerpc: include powerpc X-SVN-Group: head X-SVN-Commit-Author: jhibbits X-SVN-Commit-Paths: in head/sys/powerpc: include powerpc X-SVN-Commit-Revision: 349402 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Rspamd-Queue-Id: BF7F586721 X-Spamd-Bar: -- Authentication-Results: mx1.freebsd.org X-Spamd-Result: default: False [-2.92 / 15.00]; local_wl_from(0.00)[FreeBSD.org]; NEURAL_HAM_MEDIUM(-1.00)[-0.999,0]; NEURAL_HAM_LONG(-1.00)[-1.000,0]; NEURAL_HAM_SHORT(-0.92)[-0.919,0]; ASN(0.00)[asn:11403, ipnet:2610:1c1:1::/48, country:US] X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 26 Jun 2019 01:14:41 -0000 Author: jhibbits Date: Wed Jun 26 01:14:39 2019 New Revision: 349402 URL: https://svnweb.freebsd.org/changeset/base/349402 Log: powerpc/booke: Handle misaligned floating point loads/stores as on AIM Misaligned floating point loads and stores are already handled for AIM, but use the DSISR to obtain the necessary data. Book-E does not have the DSISR, so these fixups are not performed, leading to a SIGBUS on misaligned FP loads or stores. Obtain the necessary data on the Book-E side, similar to how is done for SPE. MFC after: 1 week Modified: head/sys/powerpc/include/trap.h head/sys/powerpc/powerpc/trap.c Modified: head/sys/powerpc/include/trap.h ============================================================================== --- head/sys/powerpc/include/trap.h Wed Jun 26 00:53:49 2019 (r349401) +++ head/sys/powerpc/include/trap.h Wed Jun 26 01:14:39 2019 (r349402) @@ -130,7 +130,7 @@ /* Macros to extract register information */ #define EXC_ALI_RST(dsisr) ((dsisr >> 5) & 0x1f) /* source or target */ #define EXC_ALI_RA(dsisr) (dsisr & 0x1f) -#define EXC_ALI_SPE_REG(instr) ((instr >> 21) & 0x1f) +#define EXC_ALI_INST_RST(instr) ((instr >> 21) & 0x1f) /* * SRR1 bits for program exception traps. These identify what caused Modified: head/sys/powerpc/powerpc/trap.c ============================================================================== --- head/sys/powerpc/powerpc/trap.c Wed Jun 26 00:53:49 2019 (r349401) +++ head/sys/powerpc/powerpc/trap.c Wed Jun 26 01:14:39 2019 (r349402) @@ -788,7 +788,7 @@ static int fix_unaligned(struct thread *td, struct trapframe *frame) { struct thread *fputhread; -#ifdef __SPE__ +#ifdef BOOKE uint32_t inst; #endif int indicator, reg; @@ -799,7 +799,7 @@ fix_unaligned(struct thread *td, struct trapframe *fra if (indicator & ESR_SPE) { if (copyin((void *)frame->srr0, &inst, sizeof(inst)) != 0) return (-1); - reg = EXC_ALI_SPE_REG(inst); + reg = EXC_ALI_INST_RST(inst); fpr = (double *)td->td_pcb->pcb_vec.vr[reg]; fputhread = PCPU_GET(vecthread); @@ -829,12 +829,22 @@ fix_unaligned(struct thread *td, struct trapframe *fra return (0); } #else +#ifdef BOOKE + indicator = (frame->cpu.booke.esr & ESR_ST) ? EXC_ALI_STFD : EXC_ALI_LFD; +#else indicator = EXC_ALI_OPCODE_INDICATOR(frame->cpu.aim.dsisr); +#endif switch (indicator) { case EXC_ALI_LFD: case EXC_ALI_STFD: +#ifdef BOOKE + if (copyin((void *)frame->srr0, &inst, sizeof(inst)) != 0) + return (-1); + reg = EXC_ALI_INST_RST(inst); +#else reg = EXC_ALI_RST(frame->cpu.aim.dsisr); +#endif fpr = &td->td_pcb->pcb_fpu.fpr[reg].fpr; fputhread = PCPU_GET(fputhread);