Date: Mon, 8 Aug 2016 13:08:55 -0600 From: Sean Bruno <sbruno@freebsd.org> To: Sreekanth Rupavatharam <rupavath@juniper.net>, "freebsd-net@freebsd.org" <freebsd-net@freebsd.org> Cc: Jack Vogel <jfvogel@gmail.com> Subject: Re: Question about em_irq_fast Message-ID: <6dd67a05-d484-593f-98f2-60a062c0daa3@freebsd.org> In-Reply-To: <C1288B46-4477-4972-92FA-F6910B3FA568@juniper.net> References: <C1288B46-4477-4972-92FA-F6910B3FA568@juniper.net>
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From: Sean Bruno <sbruno@freebsd.org>
To: Sreekanth Rupavatharam <rupavath@juniper.net>,
"freebsd-net@freebsd.org" <freebsd-net@freebsd.org>
Cc: Jack Vogel <jfvogel@gmail.com>
Message-ID: <6dd67a05-d484-593f-98f2-60a062c0daa3@freebsd.org>
Subject: Re: Question about em_irq_fast
References: <C1288B46-4477-4972-92FA-F6910B3FA568@juniper.net>
In-Reply-To: <C1288B46-4477-4972-92FA-F6910B3FA568@juniper.net>
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On 08/05/16 12:01, Sreekanth Rupavatharam wrote:
> We have this code snippet in em_irq_fast
>=20
> ifp =3D
> adapter->ifp; =20
>=20
> =
=20
>=20
> reg_icr =3D E1000_READ_REG(&adapter->hw,
> E1000_ICR); =20
>=20
> =
=20
>=20
> /* Hot eject?=20
> */ =20
>=20
> if (reg_icr =3D=3D
> 0xffffffff) =20
>=20
> return
> FILTER_STRAY; =20
>=20
> =
=20
>=20
> /* Definitely not our interrupt.=20
> */ =20
>=20
> if (reg_icr =3D=3D 0x0)
>=20
> return FILTER_STRAY; =20
>=20
> I don=E2=80=99t understand why the function returns if the read value i=
s 0. From
> the programmer=E2=80=99s manual of Intel NIC, I see the following defin=
ition.
>=20
> =20
>=20
> =20
>=20
> =09
>=20
> =20
>=20
> =09
>=20
> =20
>=20
> =09
>=20
> =20
>=20
> TXDW
>=20
> =09
>=20
> 0
>=20
> =09
>=20
> 0b
>=20
> =09
>=20
> Transmit Descriptor Written Back=E2=80=A8Set when hardware processes a =
transmit
> descriptor with the RS bit set (and possibly IDE set). If using delayed=
> interrupts (IDE set), the interrupt occurs after the timer expires.
>=20
> TXQE
>=20
> =09
>=20
> 1
>=20
> =09
>=20
> 0b
>=20
> =09
>=20
> Transmit Queue Empty
>=20
> Set when the last descriptor block for a transmit queue has been used.
>=20
> LSC
>=20
> =09
>=20
> 2
>=20
> =09
>=20
> 0b
>=20
> =09
>=20
> Link Status Change=E2=80=A8This bit is set each time the link status ch=
anges
> (either from up to
>=20
> down, or from down to up). This bit is affected by the internal link
> indication when configured for internal PHY mode.
>=20
> RXSEQ
>=20
> =09
>=20
> 3
>=20
> =09
>=20
> 0b
>=20
> =09
>=20
> Receive Sequence Error=E2=80=A8In TBI mode/internal SerDes1, incoming p=
ackets
> with a bad delimiter sequence set this bit. In other 802.3
> implementations, this would be classified as a framing error. A valid
> sequence consists of:=E2=80=A8idle =EF=82=AE SOF =EF=82=AE data =EF=82=AE=
pad (opt) EOF =EF=82=AE fill (opt) =EF=82=AE
> idle.=E2=80=A8This is a reserved bit for the *82541xx*, *82547GI/EI*, a=
nd
> *82540EP/ EM*. Set to 0b.
>=20
> RXDMT0
>=20
> =09
>=20
> 4
>=20
> =09
>=20
> 0b
>=20
> =09
>=20
> Receive Descriptor Minimum Threshold Reached
>=20
> Indicates that the minimum number of receive descriptors are available
> and software should load more receive descriptors.
>=20
> Reserved
>=20
> =09
>=20
> 5
>=20
> =09
>=20
> 0b
>=20
> =09
>=20
> Reserved Reads as 0b.
>=20
> RXO
>=20
> =09
>=20
> 6
>=20
> =09
>=20
> 0b
>=20
> =09
>=20
> Receiver Overrun=E2=80=A8Set on receive data FIFO overrun. Could be cau=
sed either
>=20
> because there are no available receive buffers or because PCI receive
> bandwidth is inadequate.
>=20
> =20
>=20
> If an interrupt happens due to a normal receive, shouldn=E2=80=99t the =
value of
> this register be 0 and still be valid? I am seeing this issue on a VM
> guest(QEMU hypervisor) where during a flood test, the driver starts
> rejecting packets because the register value is 0. Can anyone tell me
> if it=E2=80=99s ok or not to remove the check for 0 value ?
>=20
> =20
>=20
> Thanks,
>=20
> =20
>=20
> -Sreekanth
>=20
> =20
>=20
Is this with the "lem" driver or the "em" driver under QEMU?
Look for "legacy" in the boot output of your VM.
sean
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