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Date:      Tue, 14 Jul 2015 15:08:58 +0000 (UTC)
From:      Warren Block <wblock@FreeBSD.org>
To:        doc-committers@freebsd.org, svn-doc-all@freebsd.org, svn-doc-head@freebsd.org
Subject:   svn commit: r46969 - head/en_US.ISO8859-1/htdocs/news/status
Message-ID:  <201507141508.t6EF8wpw052756@repo.freebsd.org>

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Author: wblock
Date: Tue Jul 14 15:08:58 2015
New Revision: 46969
URL: https://svnweb.freebsd.org/changeset/doc/46969

Log:
  Add Konstantin Belousov <kostikbel@gmail.com>'s Cx state report.

Modified:
  head/en_US.ISO8859-1/htdocs/news/status/report-2015-04-2015-06.xml

Modified: head/en_US.ISO8859-1/htdocs/news/status/report-2015-04-2015-06.xml
==============================================================================
--- head/en_US.ISO8859-1/htdocs/news/status/report-2015-04-2015-06.xml	Tue Jul 14 14:20:28 2015	(r46968)
+++ head/en_US.ISO8859-1/htdocs/news/status/report-2015-04-2015-06.xml	Tue Jul 14 15:08:58 2015	(r46969)
@@ -971,4 +971,86 @@
       </task>
     </help>
   </project>
+
+  <project cat='kern'>
+    <title>Sleep States Enhancements on <tt>x86</tt></title>
+
+    <contact>
+      <person>
+	<name>
+	  <given>Konstantin</given>
+	  <common>Belousov</common>
+	</name>
+	<email>kib@FreeBSD.org</email>
+      </person>
+    </contact>
+
+    <links>
+      <url href="https://svnweb.freebsd.org/base?view=revision&amp;revision=282678" />
+    </links>
+
+    <body>
+      <p>The ACPI specication defines CPU Cx states, which are idle
+	states.  Methods to enter the state and miscellaneous
+	information like state leave latency are returned by the _CST
+	ACPI method.  To save energy and reduce useless heating, the
+	operating system enters the Cx state when the CPU has no work
+	to do.  C0 is the non-idle state, while C1, C2, and C3
+	(defined by ACPI) each represent an idle state with
+	sequentially more energy saving, but also with higher latency
+	of leave and possibly greater secondary costs.  For example,
+	C1 is entered by executing the HLT instruction and has no
+	architecturally visible side effects, while entering C3 drops
+	the CPU cache and usually requires special chipset programming
+	to correctly handle requests from I/O devices to the CPU.  Do
+	not confuse Cx, Px and Sx: Cx states are only meaningful when
+	the system is in fully operational state S0; Px states are
+	only meaningful when the system is not in the idle state,
+	C0.</p>
+
+      <p>Modern Intel CPUs enter Cx (x &gt;= 1) states with the
+	dedicated instruction MWAIT, which enters a specified
+	low-power state until a specific write is observed by the CPU
+	bus logic.  There is a complimentary MONITOR instruction to
+	set the monitored bus address.  The legacy port I/O method of
+	entering Cx state is emulated by CPU microcode, which
+	intercepts the port I/O and executes MWAIT internally.  Using
+	MWAIT as the method of entering Cx requires following
+	processor-specific procedures, which are communicated to the
+	operating system by the vendor-specific extensions in _CST.
+	The operating system must indicate readiness to support MWAIT
+	when calling _CST. Claimed benefits of using MWAIT are reduced
+	latencies of leaving the idle state, and visibility of more
+	deep states than defined by the common ACPI specification.
+	Still, modern Intel platforms report deep states as C2 to
+	avoid the not needed bus-mastering avoidance.</p>
+
+      <p>The new code asks ACPI for the Intel vendor-specific _CST
+	extensions, parses them, and uses MWAIT Cx entrance methods
+	when available.  The change was committed as r282678 to
+	HEAD.</p>
+
+      <p>For Linux, Intel provides a driver which does not depend on
+	the ACPI tables to use MWAIT for entering Cx states.  For all
+	Intel CPUs after Core2, the driver contains the description of
+	the Cx mode latencies and quirks, eliminating dependency on
+	the correct BIOS information, which is often incorrect.  The
+	approach of porting the Linux driver was considered by several
+	people, but all evaluators independently concluded that the
+	project cannot maintain such an approach without direct
+	involvement from Intel.</p>
+
+      <p>During the work, around 500 lines of identical code between
+	the i386 and amd64 version of the idle handling were moved to
+	the common location <tt>x86/x86/cpu_machdep.c</tt>.  Now the
+	i386 and amd64 <tt>machdep.c</tt> files contain only unique
+	machine-dependent routines.  This advance depended on John
+	Baldwin's elimination of the unmaintained Xen PVM i386
+	port.</p>
+    </body>
+
+    <sponsor>
+      The FreeBSD Foundation
+    </sponsor>
+  </project>
 </report>



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