Date: Mon, 20 Aug 2018 23:25:33 +0530 From: Rajesh Kumar <rajfbsd@gmail.com> To: gljennjohn@gmail.com Cc: freebsd-hackers@freebsd.org, marklmi26-fbsd@yahoo.com, danny@cs.huji.ac.il, freebsd-drivers@freebsd.org, ian@freebsd.org Subject: Re: Need a clarification regarding I2C bus frequency in FreeBSD Message-ID: <CAAO%2BANOFkm96HJjSTfq7=qw__L8BDFjh=ZK%2BzhYLFFkcahcE7g@mail.gmail.com> In-Reply-To: <20180820181322.71607854@ernst.home> References: <CAAO%2BANOXwXAzJt%2BBZez6422jqKjrKPboSe_%2BudnOCWxYqE-=sQ@mail.gmail.com> <1534523216.27158.17.camel@freebsd.org> <CAAO%2BANOs_YVov-d21Em1EHzajQw7wHsxkzZCnsZwkfBr2=mEiA@mail.gmail.com> <1534702861.27158.36.camel@freebsd.org> <BF721728-B6F5-4214-9180-B911D32D9FCA@cs.huji.ac.il> <A8202939-328A-4564-9CF5-F5F66F68B7B0@cs.huji.ac.il> <1534771095.27158.46.camel@freebsd.org> <35F2C250-B4CB-4C53-BF8F-43C338022E34@yahoo.com> <20180820181322.71607854@ernst.home>
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Hi, Re-posting the questions, just in case if its missed in other conversation. By "i2c clock frequency", I mean the internal base frequency only, which drives the chip. I thought data will be transferred on bus based on the base frequency. So, thought both bus and base frequency are same. But from what you said, seems both are different. So, based on the setting in *_HCNT/LCNT register, the bus frequency (which is the rate at which data is transferred) will change for a particular base frequency. Is that right? So, few questions here 1) As you said, we need to have a base frequency of 150 Mhz in our case. So, do we need to program that IG4_REG_CLK_PARMS to 150 Mhz (0x8F0D180)? And can this be done at the same time when programming the HCNT/LNCT registers? 2) Not sure how that 111Hz value is arrived. Can you please explain this calculation. So, that I can derive the appropriate values for HCNT/LCNT for different speeds at 150Mhz base clock. 3) "Default HCNT/LCNT register values would be consistent with an internal base clock speed of 1GHz", Does it mean with those values, all speeds can be achieved until 1GHz clock? On Mon, Aug 20, 2018 at 9:43 PM Gary Jennejohn <gljennjohn@gmail.com> wrote: > On Mon, 20 Aug 2018 07:16:15 -0700 > Mark Millard via freebsd-hackers <freebsd-hackers@freebsd.org> wrote: > > > On 2018-Aug-20, at 6:18 AM, Ian Lepore <ian at freebsd.org> wrote: > > > > > On Mon, 2018-08-20 at 11:13 +0300, Daniel Braniss wrote: > > >> > > >>> > > >>> On 20 Aug 2018, at 09:49, Daniel Braniss <danny@cs.huji.ac.il> > wrote: > > >>> > > >>>> . . . > > >>> > > >>> hi, > > >>> I have similar issues with the allwinner/twsi but I do have a Saleae > Logic and here is a nice picture: > > >> ah, maybe this is better: > > >> > https://cs.huji.ac.il/~danny/Screen%20Shot%202018-08-20%20at%2011.06.43.png > > > > . . . > > > This has nothing to do with the twsi driver, this is about the ig4 > > > driver (found in sys/dev/ichiic). > > > > > > That screenshot seems to show a bus running at 100KHz like it should > > > (although the 62:38 duty cycle is a bit suspicious). > > > > Being a logic analyzer display, it my just be that the threshold > > was off from the optimal value. The waveform shape is not really > > visible. > > > > The logic analyzer output also shows a thick "rising" edge without the > > uparrow symbol. My guess would be that is a rising/falling/rising > > sequence that on the scale in use does not show space between edges. In > > other words: a glitch on the leading edge side of the intended pulse. > > This too might be tied to the threshold used vs . the actual signal > > properties: no way to tell from what is shown. > > > > I have two of these logic analyzers and they definitely do a > major clean up of the signals displayed. > > Things like overshoot and ringing, which can be seen on an > oscilloscope, do not appear on what the logic analyzer displays. > > I suspect the purpose of the trace was simply to show the 100KHz > SCL. > > -- > Gary Jennejohn >
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