From owner-svn-src-all@FreeBSD.ORG Sun May 2 03:19:17 2010 Return-Path: Delivered-To: svn-src-all@FreeBSD.org Received: from mx1.freebsd.org (mx1.freebsd.org [69.147.83.52]) by hub.freebsd.org (Postfix) with ESMTP id 2676D1065672; Sun, 2 May 2010 03:19:17 +0000 (UTC) (envelope-from doconnor@gsoft.com.au) Received: from cain.gsoft.com.au (cain.gsoft.com.au [203.31.81.10]) by mx1.freebsd.org (Postfix) with ESMTP id 916038FC14; Sun, 2 May 2010 03:19:16 +0000 (UTC) Received: from [10.0.2.78] (ppp121-45-159-77.lns6.adl6.internode.on.net [121.45.159.77]) (authenticated bits=0) by cain.gsoft.com.au (8.14.4/8.14.3) with ESMTP id o423Iq1Y054159 (version=TLSv1/SSLv3 cipher=AES128-SHA bits=128 verify=NO); Sun, 2 May 2010 12:48:59 +0930 (CST) (envelope-from doconnor@gsoft.com.au) Mime-Version: 1.0 (Apple Message framework v1078) Content-Type: text/plain; charset=us-ascii From: "Daniel O'Connor" In-Reply-To: <20100501.194758.49280345204940330.imp@bsdimp.com> Date: Sun, 2 May 2010 12:48:52 +0930 Content-Transfer-Encoding: quoted-printable Message-Id: <383911EE-5844-4673-BAA8-796DDEBC5D5C@gsoft.com.au> References: <201005011636.o41GaFsK084343@svn.freebsd.org> <9624CC6A-EEB1-4492-9E62-7ACD0BF6F39C@gsoft.com.au> <20100501.194758.49280345204940330.imp@bsdimp.com> To: "M. Warner Losh" X-Mailer: Apple Mail (2.1078) X-Spam-Score: 0.163 () BAYES_00,RDNS_DYNAMIC X-Scanned-By: MIMEDefang 2.67 on 203.31.81.10 Cc: svn-src-head@FreeBSD.org, svn-src-all@FreeBSD.org, src-committers@FreeBSD.org Subject: Re: svn commit: r207472 - in head/sys: conf dev/ath/ath_hal/ar5212 X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 02 May 2010 03:19:17 -0000 On 02/05/2010, at 11:17 AM, M. Warner Losh wrote: > : Could you do TUNABLE_INT in the MIPS code and TUNABLE_INT_FETCH in = ath_hal? >=20 > How is that better than a kernel option? The only place this would > ever happen is atheros AR71xx SoC. It isn't like some of the Atheros > 71xx SoCs would have it and some wouldn't. OK. > And besides, kenv has to be compiled into the kernel on MIPS these > days... Ahh that makes a tunable fairly useless then :) > The only thing close to an idea I've had is to add: >=20 > __weak int > ath_needs_dma_war() > { > return 0; > } >=20 > and have this in the mips: >=20 > int needs_ath_dma_war =3D 0; > __weak int ath_needs_dma_war() > { > return needs_ath_dma_war; > } >=20 > and set it to 1 in the AR71xx CPU initialization. But that seemed > kind of lame... It does have the advantage of not requiring the user to do anything = which is nice even if it's clunky looking. -- Daniel O'Connor software and network engineer for Genesis Software - http://www.gsoft.com.au "The nice thing about standards is that there are so many of them to choose from." -- Andrew Tanenbaum GPG Fingerprint - 5596 B766 97C0 0E94 4347 295E E593 DC20 7B3F CE8C