From owner-freebsd-arm@FreeBSD.ORG Sun Oct 20 16:13:35 2013 Return-Path: Delivered-To: freebsd-arm@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTP id 11D5A9A6; Sun, 20 Oct 2013 16:13:35 +0000 (UTC) (envelope-from markm@FreeBSD.org) Received: from gromit.grondar.org (grandfather.grondar.org [IPv6:2a01:348:0:15:5d59:5c20:0:2]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.freebsd.org (Postfix) with ESMTPS id C9EC620E7; Sun, 20 Oct 2013 16:13:34 +0000 (UTC) Received: from graveyard.grondar.org ([88.96.155.33] helo=gronkulator.grondar.org) by gromit.grondar.org with esmtpsa (TLSv1:AES128-SHA:128) (Exim 4.80.1 (FreeBSD)) (envelope-from ) id 1VXvdD-0001xU-Tk; Sun, 20 Oct 2013 17:13:33 +0100 From: Mark Robert Vaughan Murray Content-Type: multipart/signed; boundary="Apple-Mail=_E99821B8-0642-4A65-9C48-B0CF61B5C7EE"; protocol="application/pgp-signature"; micalg=pgp-sha512 Date: Sun, 20 Oct 2013 17:13:31 +0100 Subject: ARM counter registers and get_cyclecount() To: freebsd-arm Message-Id: <0D53AF4E-9EC4-42E1-8D9E-1ECB87A9CCE6@FreeBSD.org> Mime-Version: 1.0 (Mac OS X Mail 6.6 \(1510\)) X-Mailer: Apple Mail (2.1510) X-SA-Score: -1.0 X-BeenThere: freebsd-arm@freebsd.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: Porting FreeBSD to the StrongARM Processor List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 20 Oct 2013 16:13:35 -0000 --Apple-Mail=_E99821B8-0642-4A65-9C48-B0CF61B5C7EE Content-Type: multipart/mixed; boundary="Apple-Mail=_92E64D00-B74B-488C-B31F-CFD2CA82718B" --Apple-Mail=_92E64D00-B74B-488C-B31F-CFD2CA82718B Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=us-ascii Hi folks I asked a similar question to this a month or so ago, then got involved = in other work, so apologies for the repetition! The random(4) device benefits from having a decent hardware = get_cyclecount() implementation. In i386 and arm, we have a stopgap = version that uses binuptime(), which is slow and prone to quantisation = error. I've hacked up a minimalist hardware version for ARMv6/RPI (which is the = only ARM I have access to, and I'm keen to use it for other things as = well), and I'm looking for improvement advice and/or commit blessing. Things it could conceivably do better: 1) The counter is 32 bits only. At clocks of hundreds-of-megahertz, this = will overflow in some 10's of seconds to maybe a minute, so it would be = nice (but to essential) to trap the overflow with an interrupt and = increment an upper-half counter, making a 64-bit counter. 2) Set up the debug/profile/counter registers as some kind of device = (suggestion from a couple of months back that I have no more information = on)? 3) Support more ARM arches in a more general way? I have very little ARM = hardware (only other is a BeagleBoard-xM) to test/develop this on. Anyone interested in helping me or taking this over? :-) M --=20 Mark R V Murray --Apple-Mail=_92E64D00-B74B-488C-B31F-CFD2CA82718B Content-Disposition: attachment; filename=arm.diff Content-Type: application/octet-stream; name="arm.diff" Content-Transfer-Encoding: 7bit Index: sys/arm/arm/locore.S =================================================================== --- sys/arm/arm/locore.S (revision 256775) +++ sys/arm/arm/locore.S (working copy) @@ -175,6 +175,18 @@ mcr p15, 0, r0, c13, c0, 1 /* Set ASID to 0 */ #endif +#if defined(CPU_CORTEXA) + /* TODO: Better to do access to these counters as some kind of device? + * This is 32 bits. Use interrupt to make 64 bits? Random number generator + * doesn't care, but others might. See get_cyclecount(). + */ + + mov r7, #0x8000000F /* Set INTENS to 0 to block interrupts */ + mcr p15, 0, r7, c9, c14, 2 + mov r7, #1 /* Set PMNC[0] to 1 to enable CCNT */ + mcr p15, 0, r7, c9, c12, 0 +#endif + /* Set the Domain Access register. Very important! */ mov r0, #((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT) mcr p15, 0, r0, c3, c0, 0 Index: sys/arm/include/cpu.h =================================================================== --- sys/arm/include/cpu.h (revision 256775) +++ sys/arm/include/cpu.h (working copy) @@ -13,11 +13,21 @@ static __inline uint64_t get_cyclecount(void) { +#if defined(CPU_CORTEXA) + uint32_t ccnt; + + /* + * Read CCNT. Curses! Its only 32 bits. + * Fix this catching overflow with interrupt in locore.S? + */ + __asm __volatile("mrc p15, 0, %0, c9, c13, 0": "=r" (ccnt)); + return ((uint64_t)ccnt); +#else struct bintime bt; binuptime(&bt); return ((uint64_t)bt.sec << 56 | bt.frac >> 8); - +#endif } #endif --Apple-Mail=_92E64D00-B74B-488C-B31F-CFD2CA82718B Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset=us-ascii --Apple-Mail=_92E64D00-B74B-488C-B31F-CFD2CA82718B-- --Apple-Mail=_E99821B8-0642-4A65-9C48-B0CF61B5C7EE Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename=signature.asc Content-Type: application/pgp-signature; name=signature.asc Content-Description: Message signed with OpenPGP using GPGMail -----BEGIN PGP SIGNATURE----- Version: GnuPG/MacGPG2 v2.0.20 (Darwin) Comment: GPGTools - http://gpgtools.org iQCVAwUBUmQBK958vKOKE6LNAQpFsQP9HFU1je1H+A+xNWudnwBnzfQ3B4XKeD1T qP8hcUNj+mEwlrF+R0HU38k0gAPgGIJw0L9jNTapMonvE56vKrphfKqf8RSfBs3b LYN2FpVIX7ciFV7zzT1cBZB7YHhWSvE5q4Xx2ekU2ldU0DKJ3eZKAOgHnwbRu0TO 77NiU50LnVE= =6JGW -----END PGP SIGNATURE----- --Apple-Mail=_E99821B8-0642-4A65-9C48-B0CF61B5C7EE--