From owner-svn-src-all@freebsd.org Wed Feb 3 16:44:08 2016 Return-Path: Delivered-To: svn-src-all@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 720C0A9AB44; Wed, 3 Feb 2016 16:44:08 +0000 (UTC) (envelope-from mmel@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 2DC4B12BF; Wed, 3 Feb 2016 16:44:08 +0000 (UTC) (envelope-from mmel@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id u13Gi7AC012835; Wed, 3 Feb 2016 16:44:07 GMT (envelope-from mmel@FreeBSD.org) Received: (from mmel@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id u13Gi6Yw012828; Wed, 3 Feb 2016 16:44:06 GMT (envelope-from mmel@FreeBSD.org) Message-Id: <201602031644.u13Gi6Yw012828@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: mmel set sender to mmel@FreeBSD.org using -f From: Michal Meloun Date: Wed, 3 Feb 2016 16:44:06 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r295213 - in head/sys/arm: arm at91 cavium/cns11xx include xscale/i8134x xscale/ixp425 xscale/pxa X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 03 Feb 2016 16:44:08 -0000 Author: mmel Date: Wed Feb 3 16:44:06 2016 New Revision: 295213 URL: https://svnweb.freebsd.org/changeset/base/295213 Log: ARM: Consistently use cpu_setttb() instead of setttb(). Remove unused #define for drain_writebuf. Modified: head/sys/arm/arm/machdep.c head/sys/arm/at91/at91_machdep.c head/sys/arm/cavium/cns11xx/econa_machdep.c head/sys/arm/include/cpufunc.h head/sys/arm/xscale/i8134x/crb_machdep.c head/sys/arm/xscale/ixp425/avila_machdep.c head/sys/arm/xscale/pxa/pxa_machdep.c Modified: head/sys/arm/arm/machdep.c ============================================================================== --- head/sys/arm/arm/machdep.c Wed Feb 3 15:45:13 2016 (r295212) +++ head/sys/arm/arm/machdep.c Wed Feb 3 16:44:06 2016 (r295213) @@ -1622,7 +1622,7 @@ initarm(struct arm_boot_params *abp) cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) | DOMAIN_CLIENT); pmap_pa = kernel_l1pt.pv_pa; - setttb(kernel_l1pt.pv_pa); + cpu_setttb(kernel_l1pt.pv_pa); cpu_tlb_flushID(); cpu_domains(DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)); @@ -1675,7 +1675,7 @@ initarm(struct arm_boot_params *abp) /* * We must now clean the cache again.... * Cleaning may be done by reading new data to displace any - * dirty data in the cache. This will have happened in setttb() + * dirty data in the cache. This will have happened in cpu_setttb() * but since we are boot strapping the addresses used for the read * may have just been remapped and thus the cache could be out * of sync. A re-clean after the switch will cure this. @@ -1867,7 +1867,7 @@ initarm(struct arm_boot_params *abp) /* * We must now clean the cache again.... * Cleaning may be done by reading new data to displace any - * dirty data in the cache. This will have happened in setttb() + * dirty data in the cache. This will have happened in cpu_setttb() * but since we are boot strapping the addresses used for the read * may have just been remapped and thus the cache could be out * of sync. A re-clean after the switch will cure this. Modified: head/sys/arm/at91/at91_machdep.c ============================================================================== --- head/sys/arm/at91/at91_machdep.c Wed Feb 3 15:45:13 2016 (r295212) +++ head/sys/arm/at91/at91_machdep.c Wed Feb 3 16:44:06 2016 (r295213) @@ -566,7 +566,7 @@ initarm(struct arm_boot_params *abp) arm_devmap_bootstrap(l1pagetable, at91_devmap); cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) | DOMAIN_CLIENT); - setttb(kernel_l1pt.pv_pa); + cpu_setttb(kernel_l1pt.pv_pa); cpu_tlb_flushID(); cpu_domains(DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)); @@ -612,7 +612,7 @@ initarm(struct arm_boot_params *abp) /* * We must now clean the cache again.... * Cleaning may be done by reading new data to displace any - * dirty data in the cache. This will have happened in setttb() + * dirty data in the cache. This will have happened in cpu_setttb() * but since we are boot strapping the addresses used for the read * may have just been remapped and thus the cache could be out * of sync. A re-clean after the switch will cure this. Modified: head/sys/arm/cavium/cns11xx/econa_machdep.c ============================================================================== --- head/sys/arm/cavium/cns11xx/econa_machdep.c Wed Feb 3 15:45:13 2016 (r295212) +++ head/sys/arm/cavium/cns11xx/econa_machdep.c Wed Feb 3 16:44:06 2016 (r295213) @@ -275,7 +275,7 @@ initarm(struct arm_boot_params *abp) arm_devmap_bootstrap(l1pagetable, econa_devmap); cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT); - setttb(kernel_l1pt.pv_pa); + cpu_setttb(kernel_l1pt.pv_pa); cpu_tlb_flushID(); cpu_domains(DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)); cninit(); @@ -297,7 +297,7 @@ initarm(struct arm_boot_params *abp) /* * We must now clean the cache again.... * Cleaning may be done by reading new data to displace any - * dirty data in the cache. This will have happened in setttb() + * dirty data in the cache. This will have happened in cpu_setttb() * but since we are boot strapping the addresses used for the read * may have just been remapped and thus the cache could be out * of sync. A re-clean after the switch will cure this. Modified: head/sys/arm/include/cpufunc.h ============================================================================== --- head/sys/arm/include/cpufunc.h Wed Feb 3 15:45:13 2016 (r295212) +++ head/sys/arm/include/cpufunc.h Wed Feb 3 16:44:06 2016 (r295213) @@ -412,9 +412,6 @@ void xscalec3_context_switch (void); #endif /* CPU_XSCALE_81342 */ -#define setttb cpu_setttb -#define drain_writebuf cpu_drain_writebuf - /* * Macros for manipulating CPU interrupts */ Modified: head/sys/arm/xscale/i8134x/crb_machdep.c ============================================================================== --- head/sys/arm/xscale/i8134x/crb_machdep.c Wed Feb 3 15:45:13 2016 (r295212) +++ head/sys/arm/xscale/i8134x/crb_machdep.c Wed Feb 3 16:44:06 2016 (r295213) @@ -267,7 +267,7 @@ initarm(struct arm_boot_params *abp) xscale_cache_clean_addr = 0xff000000U; cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT); - setttb(kernel_l1pt.pv_pa); + cpu_setttb(kernel_l1pt.pv_pa); cpu_tlb_flushID(); cpu_domains(DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)); /* @@ -284,7 +284,7 @@ initarm(struct arm_boot_params *abp) /* * We must now clean the cache again.... * Cleaning may be done by reading new data to displace any - * dirty data in the cache. This will have happened in setttb() + * dirty data in the cache. This will have happened in cpu_setttb() * but since we are boot strapping the addresses used for the read * may have just been remapped and thus the cache could be out * of sync. A re-clean after the switch will cure this. Modified: head/sys/arm/xscale/ixp425/avila_machdep.c ============================================================================== --- head/sys/arm/xscale/ixp425/avila_machdep.c Wed Feb 3 15:45:13 2016 (r295212) +++ head/sys/arm/xscale/ixp425/avila_machdep.c Wed Feb 3 16:44:06 2016 (r295213) @@ -353,7 +353,7 @@ initarm(struct arm_boot_params *abp) xscale_cache_clean_addr = 0xff000000U; cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT); - setttb(kernel_l1pt.pv_pa); + cpu_setttb(kernel_l1pt.pv_pa); cpu_tlb_flushID(); cpu_domains(DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)); @@ -370,7 +370,7 @@ initarm(struct arm_boot_params *abp) /* * We must now clean the cache again.... * Cleaning may be done by reading new data to displace any - * dirty data in the cache. This will have happened in setttb() + * dirty data in the cache. This will have happened in cpu_setttb() * but since we are boot strapping the addresses used for the read * may have just been remapped and thus the cache could be out * of sync. A re-clean after the switch will cure this. Modified: head/sys/arm/xscale/pxa/pxa_machdep.c ============================================================================== --- head/sys/arm/xscale/pxa/pxa_machdep.c Wed Feb 3 15:45:13 2016 (r295212) +++ head/sys/arm/xscale/pxa/pxa_machdep.c Wed Feb 3 16:44:06 2016 (r295213) @@ -267,7 +267,7 @@ initarm(struct arm_boot_params *abp) xscale_cache_clean_addr = 0xff000000U; cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT); - setttb(kernel_l1pt.pv_pa); + cpu_setttb(kernel_l1pt.pv_pa); cpu_tlb_flushID(); cpu_domains(DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)); @@ -284,7 +284,7 @@ initarm(struct arm_boot_params *abp) /* * We must now clean the cache again.... * Cleaning may be done by reading new data to displace any - * dirty data in the cache. This will have happened in setttb() + * dirty data in the cache. This will have happened in cpu_setttb() * but since we are boot strapping the addresses used for the read * may have just been remapped and thus the cache could be out * of sync. A re-clean after the switch will cure this.