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From: =?windows-1252?Q?Hans_Petter_Selasky?= <hans.petter.selasky@bitfrost.no>
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Date: Mon, 27 Aug 2012 08:06:57 +0200
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Cc: "=?windows-1252?Q?freebsd-arm=40freebsd.org?=" <freebsd-arm@freebsd.org>,
	"=?windows-1252?Q?freebsd-mips=40freebsd.org?=" <freebsd-mips@freebsd.org>,
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Subject: RE: Partial cacheline flush problems on ARM and MIPS
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Hi,=20=0D=0ACorrect.=0D=0A=0D=0A> We also need some rules about working w=
ith buffers obtained from=0D=0A> bus_dmamem_alloc() and external buffers =
passed to bus_dmamap_load(). =A0I=0D=0A> think the rule should be that a =
buffer obtained from bus_dmamem_alloc(),=0D=0A> or more formally any regi=
on of memory mapped by a bus_dmamap_load(), is=0D=0A> a single logical ob=
ject which can only be accessed by one entity at a=0D=0A> time. =A0That m=
eans that there cannot be two concurrent DMA operations=0D=0A> happening =
in different regions of the same buffer, nor can DMA and CPU=0D=0A> acces=
s be happening concurrently even if in different parts of the=0D=0A> buff=
er. =A0=0D=0A=0D=0A=0D=0AIs this something which we can fix using a simpl=
e __align(USB_DMA_ALIGN) on elements in C-structures which are allowed to=
 be DMA loaded.=0D=0A=0D=0A=A0=0D=0A=0D=0AAlso: Why is busdma not complai=
ning when loading a non-valid buffer pointer=3F=0D=0A=0D=0A--HPS=0D=0A