From owner-freebsd-arm@FreeBSD.ORG Tue Apr 3 16:26:37 2007 Return-Path: X-Original-To: freebsd-arm@freebsd.org Delivered-To: freebsd-arm@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [69.147.83.52]) by hub.freebsd.org (Postfix) with ESMTP id 0B3B616A409 for ; Tue, 3 Apr 2007 16:26:37 +0000 (UTC) (envelope-from mlfbsd@dong.ci0.org) Received: from dong.ci0.org (cognet.ci0.org [80.65.224.102]) by mx1.freebsd.org (Postfix) with ESMTP id 4CF5813C4BE for ; Tue, 3 Apr 2007 16:26:35 +0000 (UTC) (envelope-from mlfbsd@dong.ci0.org) Received: from dong.ci0.org (localhost.ci0.org [127.0.0.1]) by dong.ci0.org (8.13.8/8.13.8) with ESMTP id l33Gke2n015745; Tue, 3 Apr 2007 18:46:40 +0200 (CEST) (envelope-from mlfbsd@dong.ci0.org) Received: (from mlfbsd@localhost) by dong.ci0.org (8.13.8/8.13.8/Submit) id l33Gkdup015744; Tue, 3 Apr 2007 18:46:39 +0200 (CEST) (envelope-from mlfbsd) Date: Tue, 3 Apr 2007 18:46:39 +0200 From: Olivier Houchard To: ticso@cicely.de Message-ID: <20070403164639.GA15510@ci0.org> References: <20070403154858.GR80382@cicely12.cicely.de> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20070403154858.GR80382@cicely12.cicely.de> User-Agent: Mutt/1.4.1i Cc: Bernd Walter , freebsd-arm@freebsd.org Subject: Re: adding 16550 UART to RM9200 X-BeenThere: freebsd-arm@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Porting FreeBSD to the StrongARM Processor List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 03 Apr 2007 16:26:37 -0000 Hi, On Tue, Apr 03, 2007 at 05:48:58PM +0200, Bernd Walter wrote: > I plan to add up to 48 16550 UART to an RM9200 system. > It should be done with 16C554 chips - so I only have 16 byte FiFo. > I would like to avoid using 64 byte FiFo chips, but those are pin > compatible, so things are changeable in case. > Likely most of the ports are doing low volume and I hope this will > be Ok. > They will be addressed via NCS2 space. > Most of the external interrupts are not available because of > unfortunate multiplexing with other required signals, so I have to > attach them all to IRQ0. > The interrupt will be level configured by firmware. > And the NCS2 waitstates and buswidth will be configured by firmware > as well. > > However some question points are still left: > > - How can I attach our uart(4) driver to the chips? > It will likely addressed with: > UART0 0x30000000 - 0x30000007 IRQ0 > UART1 0x30000008 - 0x3000000f IRQ0 > UART2 0x30000010 - 0x30000017 IRQ0 > UART3 0x30000018 - 0x3000001f IRQ0 > UART4 0x30000020 - 0x30000027 IRQ0 > UART5 0x30000028 - 0x3000002f IRQ0 > [...] > UART47 0x30000170 - 0x30000177 IRQ0 > UART48 0x30000178 - 0x3000017f IRQ0 > I think you'll want to use hints. > - I would like to use a 14,7456MHz xtal > How can I tell uart(4) the frequency? > You can play with the struct uart_devinfo.bas.rclk field. > - How can I configure NCS2 range as being uncacheable? > I asume this has to be done somehow in the kernel. > pmap_mapdev() maps the physical range passed uncached, so you can use it. Cheers, Olivier