From owner-freebsd-arch@FreeBSD.ORG Thu Jun 12 02:21:05 2003 Return-Path: Delivered-To: freebsd-arch@freebsd.org Received: from mx1.FreeBSD.org (mx1.freebsd.org [216.136.204.125]) by hub.freebsd.org (Postfix) with ESMTP id 530A237B401 for ; Thu, 12 Jun 2003 02:21:05 -0700 (PDT) Received: from mail.chesapeake.net (chesapeake.net [208.142.252.6]) by mx1.FreeBSD.org (Postfix) with ESMTP id 5565C43FAF for ; Thu, 12 Jun 2003 02:21:04 -0700 (PDT) (envelope-from jroberson@chesapeake.net) Received: from localhost (jroberson@localhost) by mail.chesapeake.net (8.11.6/8.11.6) with ESMTP id h5C9L3E64375 for ; Thu, 12 Jun 2003 05:21:03 -0400 (EDT) (envelope-from jroberson@chesapeake.net) Date: Thu, 12 Jun 2003 05:21:03 -0400 (EDT) From: Jeff Roberson To: arch@freebsd.org Message-ID: <20030612051553.J36168-100000@mail.chesapeake.net> MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Subject: HyperThreading and CPU topologies. X-BeenThere: freebsd-arch@freebsd.org X-Mailman-Version: 2.1.1 Precedence: list List-Id: Discussion related to FreeBSD architecture List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 12 Jun 2003 09:21:05 -0000 While I was at USENIX I started implementing HTT support in ULE. To do this I needed a way for the machine dependant code to tell the MI code about the CPU topology. I decided to make this generic enough to handle architectures more complicated than a few HTT capable cores. What I came up with can be used to describe N tiers of CPU groups each containing a variable number of processors. For the Hyper threading case you make one level of groups that each have all of the logical cores for one physical cpu in that group. For something like NUMA you would have one group for each node and one group for each CPU in that node. This is different from HTT where you have one group for each physical cpu. Below I'll supply the patch for sys/smp.h. One thing to note is that I intend for the smp_topology to be optional. If it is not supplied strict SMP will be assumed. That way MD code for all architectures doesn't have to be updated. Just those who support HTT (Or some other SMT implementation) or NUMA (hah). Here's the structures: Index: smp.h =================================================================== RCS file: /home/ncvs/src/sys/sys/smp.h,v retrieving revision 1.72 diff -r1.72 smp.h 19a20,46 > > /* > * Topology of a NUMA or HTT system. > * > * The top level topology is an array of pointers to groups. Each group > * contains a bitmask of cpus in its group or subgroups. It may also > * contain a pointer to an array of child groups. > * > * The bitmasks at non leaf groups may be used by consumers who support > * a smaller depth than the hardware provides. > * > * The topology may be omitted by systems where all CPUs are equal. > */ > > struct cpu_group { > int cg_mask; /* Mask of cpus in this group. */ > int cg_count; /* Count of cpus in this group. */ > int cg_children; /* Number of children groups. */ > struct cpu_group **cg_child; /* Optional child group. */ > }; > > struct cpu_top { > int ct_count; /* Count of groups. */ > struct cpu_group **ct_group; /* Array of pointers to cpu groups. */ > }; > > extern struct cpu_top *smp_topology; Cheers, Jeff