From nobody Wed Jul 6 17:32:47 2022 X-Original-To: dev-commits-src-all@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id 67A0F1D12167; Wed, 6 Jul 2022 17:32:47 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "R3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 4LdRSv29f3z3L3V; Wed, 6 Jul 2022 17:32:47 +0000 (UTC) (envelope-from git@FreeBSD.org) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1657128767; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=pbWCr2PQ8fPrcLASX4nBuv10fodkAmdUKT5BiHTz6dE=; b=G2XZSxw3xsW71j9DEJb4rbFWFXW0kUlB9pAHjakQ42u7VqIy0Rr311kJ0gmwHVyaaBPr1e VTKLnXJZ0w/kfKic937F+tYyiMU9wvRAd6pzbWyp8yWvA+Id+dMwcpb9jQDDBDELMJ/x+Y fPqoBq3gPSNhm/AD+N2ewT8+oG0ozU2sarqZoqQcopoLcu/Pc07PHc5Vx28Hv2qZ3zSd1V iZHaUgCEvrPEOLrux+Rk2EdLvXCKeVBKLAdoIaELbzD2cChMVD4VP4o6cMF9IHnhwpDbus tY4yEKrest9mJAARlFiUQsPff2ZTrXfsP0+EIzh5QSeObNfI5Bf78/1EEGC27g== Received: from gitrepo.freebsd.org (gitrepo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:5]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 2ACF01EDBA; Wed, 6 Jul 2022 17:32:47 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from gitrepo.freebsd.org ([127.0.1.44]) by gitrepo.freebsd.org (8.16.1/8.16.1) with ESMTP id 266HWliT024183; Wed, 6 Jul 2022 17:32:47 GMT (envelope-from git@gitrepo.freebsd.org) Received: (from git@localhost) by gitrepo.freebsd.org (8.16.1/8.16.1/Submit) id 266HWlSw024182; Wed, 6 Jul 2022 17:32:47 GMT (envelope-from git) Date: Wed, 6 Jul 2022 17:32:47 GMT Message-Id: <202207061732.266HWlSw024182@gitrepo.freebsd.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-main@FreeBSD.org From: Mitchell Horne Subject: git: 9d97138e2d13 - main - libpmc: import updated pmu-events for arm64 List-Id: Commit messages for all branches of the src repository List-Archive: https://lists.freebsd.org/archives/dev-commits-src-all List-Help: List-Post: List-Subscribe: List-Unsubscribe: Sender: owner-dev-commits-src-all@freebsd.org X-BeenThere: dev-commits-src-all@freebsd.org MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Git-Committer: mhorne X-Git-Repository: src X-Git-Refname: refs/heads/main X-Git-Reftype: branch X-Git-Commit: 9d97138e2d138bcd03dc28f45e78b13c536bed84 Auto-Submitted: auto-generated ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1657128767; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=pbWCr2PQ8fPrcLASX4nBuv10fodkAmdUKT5BiHTz6dE=; b=e5T/NF2JvRXoV/0W14EjPGbRs+TqnTv6B8xBNYRO8Aj/xGhc99YmTmo4K0910xIzhTArGM uZzePxSaFWmutDmsif/4STm99TbPo3TqVfuRJd7z/pqJ6wW2EFD43+cM1V7gWBsCmdr/AO upMn1K5Iw6cGo/X/XU+wDQBBpau0RJtIROlBOsUPnIFoSemHkHcDZNJQNXVTocs9AX1fOW JuaKl9NA4jBpd6jOH0a+BrY4zKF+4CuKZdJ/n0McBCqdidqF0Z4dZgd6tGxsC4lyejuEGH g8xZyzcLEan0yXs6AGUaJyzkSnLQdYuSdsu5cIAEVeVEfxDAGwLLKzje8MPCPA== ARC-Seal: i=1; s=dkim; d=freebsd.org; t=1657128767; a=rsa-sha256; cv=none; b=q8pnlZGq0en3kNbnGbccNYQbLUnnSgY6zW6acKVo5SKCoZ08KZdJtXul+i29ltHSkch3U8 UrKLWVVJAcaa8Njbs8fOs7PzFGEa7gjXe+8HbAd38el9jMfo/hw8bGaQvoRLd8t1HH26a7 JxG7rUTOzvKxN8xBv00ebFCbcWOzUi2ZRai3NxlQ6NM7Z3gLonplv5NQOuO4lBtz+1uqkG xENyHmjU0HunZEH0q3V939QRenXWFglhGCizO0EjYCKoBT9KvWRnHhtFk2NgxQikI8iF2Y 8cJtnQYDl+gTd1yiq70ikMILErw87qw8j9V/jmBMK/fWU5U6ursXlPML3qLS4w== ARC-Authentication-Results: i=1; mx1.freebsd.org; none X-ThisMailContainsUnwantedMimeParts: N The branch main has been updated by mhorne: URL: https://cgit.FreeBSD.org/src/commit/?id=9d97138e2d138bcd03dc28f45e78b13c536bed84 commit 9d97138e2d138bcd03dc28f45e78b13c536bed84 Author: Mitchell Horne AuthorDate: 2022-07-06 17:29:55 +0000 Commit: Mitchell Horne CommitDate: 2022-07-06 17:32:21 +0000 libpmc: import updated pmu-events for arm64 Thanks to the recently updated import of the jevents utility by mav@, we can now compile the latest version of these event definitions. This should support a wider set of common ARMv8 processors, for example, the Cortex-A72 in the Raspberry Pi 4. This brings this folder in sync with Linux commit 62e6eb8d5454. Reviewed by: emaste Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D35549 --- .../pmu-events/arch/arm64/ampere/emag/branch.json | 19 + .../pmu-events/arch/arm64/ampere/emag/bus.json | 23 + .../pmu-events/arch/arm64/ampere/emag/cache.json | 161 ++++ .../pmu-events/arch/arm64/ampere/emag/clock.json | 18 + .../arch/arm64/ampere/emag/exception.json | 44 ++ .../arch/arm64/ampere/emag/instruction.json | 73 ++ .../arch/arm64/ampere/emag/intrinsic.json | 14 + .../pmu-events/arch/arm64/ampere/emag/memory.json | 24 + .../arch/arm64/ampere/emag/pipeline.json | 50 ++ .../arch/arm64/arm/cortex-a34/branch.json | 11 + .../pmu-events/arch/arm64/arm/cortex-a34/bus.json | 17 + .../arch/arm64/arm/cortex-a34/cache.json | 32 + .../arch/arm64/arm/cortex-a34/exception.json | 14 + .../arch/arm64/arm/cortex-a34/instruction.json | 29 + .../arch/arm64/arm/cortex-a34/memory.json | 8 + .../arch/arm64/arm/cortex-a35/branch.json | 11 + .../pmu-events/arch/arm64/arm/cortex-a35/bus.json | 17 + .../arch/arm64/arm/cortex-a35/cache.json | 32 + .../arch/arm64/arm/cortex-a35/exception.json | 14 + .../arch/arm64/arm/cortex-a35/instruction.json | 44 ++ .../arch/arm64/arm/cortex-a35/memory.json | 8 + .../arch/arm64/arm/cortex-a510/branch.json | 59 ++ .../pmu-events/arch/arm64/arm/cortex-a510/bus.json | 17 + .../arch/arm64/arm/cortex-a510/cache.json | 182 +++++ .../arch/arm64/arm/cortex-a510/exception.json | 14 + .../arch/arm64/arm/cortex-a510/instruction.json | 95 +++ .../arch/arm64/arm/cortex-a510/memory.json | 32 + .../arch/arm64/arm/cortex-a510/pipeline.json | 107 +++ .../pmu-events/arch/arm64/arm/cortex-a510/pmu.json | 8 + .../arch/arm64/arm/cortex-a510/trace.json | 32 + .../arch/arm64/arm/cortex-a55/branch.json | 59 ++ .../pmu-events/arch/arm64/arm/cortex-a55/bus.json | 17 + .../arch/arm64/arm/cortex-a55/cache.json | 188 +++++ .../arch/arm64/arm/cortex-a55/exception.json | 20 + .../arch/arm64/arm/cortex-a55/instruction.json | 65 ++ .../arch/arm64/arm/cortex-a55/memory.json | 17 + .../arch/arm64/arm/cortex-a55/pipeline.json | 80 ++ .../arch/arm64/arm/cortex-a57-a72/branch.json | 17 + .../arch/arm64/arm/cortex-a57-a72/bus.json | 29 + .../arch/arm64/arm/cortex-a57-a72/cache.json | 80 ++ .../arch/arm64/arm/cortex-a57-a72/exception.json | 47 ++ .../arch/arm64/arm/cortex-a57-a72/instruction.json | 68 ++ .../arch/arm64/arm/cortex-a57-a72/memory.json | 20 + .../arch/arm64/arm/cortex-a65/branch.json | 17 + .../pmu-events/arch/arm64/arm/cortex-a65/bus.json | 17 + .../arch/arm64/arm/cortex-a65/cache.json | 236 ++++++ .../pmu-events/arch/arm64/arm/cortex-a65/dpu.json | 32 + .../arch/arm64/arm/cortex-a65/exception.json | 14 + .../pmu-events/arch/arm64/arm/cortex-a65/ifu.json | 122 ++++ .../arch/arm64/arm/cortex-a65/instruction.json | 71 ++ .../arch/arm64/arm/cortex-a65/memory.json | 35 + .../arch/arm64/arm/cortex-a65/pipeline.json | 8 + .../arch/arm64/arm/cortex-a710/branch.json | 17 + .../pmu-events/arch/arm64/arm/cortex-a710/bus.json | 20 + .../arch/arm64/arm/cortex-a710/cache.json | 155 ++++ .../arch/arm64/arm/cortex-a710/exception.json | 47 ++ .../arch/arm64/arm/cortex-a710/instruction.json | 134 ++++ .../arch/arm64/arm/cortex-a710/memory.json | 41 ++ .../arch/arm64/arm/cortex-a710/pipeline.json | 23 + .../arch/arm64/arm/cortex-a710/trace.json | 29 + .../arch/arm64/arm/cortex-a73/branch.json | 11 + .../pmu-events/arch/arm64/arm/cortex-a73/bus.json | 23 + .../arch/arm64/arm/cortex-a73/cache.json | 107 +++ .../pmu-events/arch/arm64/arm/cortex-a73/etm.json | 14 + .../arch/arm64/arm/cortex-a73/exception.json | 14 + .../arch/arm64/arm/cortex-a73/instruction.json | 65 ++ .../arch/arm64/arm/cortex-a73/memory.json | 14 + .../pmu-events/arch/arm64/arm/cortex-a73/mmu.json | 44 ++ .../arch/arm64/arm/cortex-a73/pipeline.json | 38 + .../arch/arm64/arm/cortex-a75/branch.json | 11 + .../pmu-events/arch/arm64/arm/cortex-a75/bus.json | 17 + .../arch/arm64/arm/cortex-a75/cache.json | 164 +++++ .../pmu-events/arch/arm64/arm/cortex-a75/etm.json | 14 + .../arch/arm64/arm/cortex-a75/exception.json | 17 + .../arch/arm64/arm/cortex-a75/instruction.json | 74 ++ .../arch/arm64/arm/cortex-a75/memory.json | 17 + .../pmu-events/arch/arm64/arm/cortex-a75/mmu.json | 44 ++ .../arch/arm64/arm/cortex-a75/pipeline.json | 44 ++ .../arch/arm64/arm/cortex-a76-n1/branch.json | 10 + .../arch/arm64/arm/cortex-a76-n1/bus.json | 21 + .../arch/arm64/arm/cortex-a76-n1/cache.json | 169 +++++ .../arch/arm64/arm/cortex-a76-n1/exception.json | 48 ++ .../arch/arm64/arm/cortex-a76-n1/instruction.json | 91 +++ .../arch/arm64/arm/cortex-a76-n1/memory.json | 21 + .../arch/arm64/arm/cortex-a76-n1/other.json | 5 + .../arch/arm64/arm/cortex-a76-n1/pipeline.json | 10 + .../arch/arm64/arm/cortex-a77/branch.json | 17 + .../pmu-events/arch/arm64/arm/cortex-a77/bus.json | 17 + .../arch/arm64/arm/cortex-a77/cache.json | 143 ++++ .../arch/arm64/arm/cortex-a77/exception.json | 47 ++ .../arch/arm64/arm/cortex-a77/instruction.json | 77 ++ .../arch/arm64/arm/cortex-a77/memory.json | 23 + .../arch/arm64/arm/cortex-a77/pipeline.json | 8 + .../arch/arm64/arm/cortex-a78/branch.json | 17 + .../pmu-events/arch/arm64/arm/cortex-a78/bus.json | 20 + .../arch/arm64/arm/cortex-a78/cache.json | 155 ++++ .../arch/arm64/arm/cortex-a78/exception.json | 47 ++ .../arch/arm64/arm/cortex-a78/instruction.json | 80 ++ .../arch/arm64/arm/cortex-a78/memory.json | 23 + .../arch/arm64/arm/cortex-a78/pipeline.json | 23 + .../arch/arm64/arm/cortex-x1/branch.json | 17 + .../pmu-events/arch/arm64/arm/cortex-x1/bus.json | 20 + .../pmu-events/arch/arm64/arm/cortex-x1/cache.json | 155 ++++ .../arch/arm64/arm/cortex-x1/exception.json | 47 ++ .../arch/arm64/arm/cortex-x1/instruction.json | 80 ++ .../arch/arm64/arm/cortex-x1/memory.json | 23 + .../arch/arm64/arm/cortex-x1/pipeline.json | 23 + .../arch/arm64/arm/cortex-x2/branch.json | 17 + .../pmu-events/arch/arm64/arm/cortex-x2/bus.json | 20 + .../pmu-events/arch/arm64/arm/cortex-x2/cache.json | 155 ++++ .../arch/arm64/arm/cortex-x2/exception.json | 47 ++ .../arch/arm64/arm/cortex-x2/instruction.json | 134 ++++ .../arch/arm64/arm/cortex-x2/memory.json | 41 ++ .../arch/arm64/arm/cortex-x2/pipeline.json | 23 + .../pmu-events/arch/arm64/arm/cortex-x2/trace.json | 29 + .../arch/arm64/arm/neoverse-e1/branch.json | 17 + .../pmu-events/arch/arm64/arm/neoverse-e1/bus.json | 17 + .../arch/arm64/arm/neoverse-e1/cache.json | 107 +++ .../arch/arm64/arm/neoverse-e1/exception.json | 14 + .../arch/arm64/arm/neoverse-e1/instruction.json | 65 ++ .../arch/arm64/arm/neoverse-e1/memory.json | 23 + .../arch/arm64/arm/neoverse-e1/pipeline.json | 8 + .../pmu-events/arch/arm64/arm/neoverse-e1/spe.json | 14 + .../arch/arm64/arm/neoverse-n2/branch.json | 8 + .../pmu-events/arch/arm64/arm/neoverse-n2/bus.json | 20 + .../arch/arm64/arm/neoverse-n2/cache.json | 155 ++++ .../arch/arm64/arm/neoverse-n2/exception.json | 47 ++ .../arch/arm64/arm/neoverse-n2/instruction.json | 143 ++++ .../arch/arm64/arm/neoverse-n2/memory.json | 38 + .../arch/arm64/arm/neoverse-n2/other.json | 5 + .../arch/arm64/arm/neoverse-n2/pipeline.json | 23 + .../pmu-events/arch/arm64/arm/neoverse-n2/spe.json | 14 + .../arch/arm64/arm/neoverse-n2/trace.json | 29 + .../arch/arm64/arm/neoverse-v1/branch.json | 8 + .../pmu-events/arch/arm64/arm/neoverse-v1/bus.json | 20 + .../arch/arm64/arm/neoverse-v1/cache.json | 155 ++++ .../arch/arm64/arm/neoverse-v1/exception.json | 47 ++ .../arch/arm64/arm/neoverse-v1/instruction.json | 89 +++ .../arch/arm64/arm/neoverse-v1/memory.json | 20 + .../arch/arm64/arm/neoverse-v1/other.json | 5 + .../arch/arm64/arm/neoverse-v1/pipeline.json | 23 + .../arch/arm64/cavium/thunderx2/core-imp-def.json | 87 ++- .../arch/arm64/common-and-microarch.json | 812 +++++++++++++++++++++ .../arch/arm64/freescale/imx8mm/sys/ddrc.json | 39 + .../arch/arm64/freescale/imx8mm/sys/metrics.json | 18 + .../arch/arm64/freescale/imx8mn/sys/ddrc.json | 37 + .../arch/arm64/freescale/imx8mn/sys/metrics.json | 18 + .../arch/arm64/freescale/imx8mp/sys/ddrc.json | 37 + .../arch/arm64/freescale/imx8mp/sys/metrics.json | 466 ++++++++++++ .../arch/arm64/freescale/imx8mq/sys/ddrc.json | 37 + .../arch/arm64/freescale/imx8mq/sys/metrics.json | 18 + .../arch/arm64/fujitsu/a64fx/branch.json | 8 + .../pmu-events/arch/arm64/fujitsu/a64fx/bus.json | 62 ++ .../pmu-events/arch/arm64/fujitsu/a64fx/cache.json | 128 ++++ .../pmu-events/arch/arm64/fujitsu/a64fx/cycle.json | 5 + .../arch/arm64/fujitsu/a64fx/exception.json | 29 + .../arch/arm64/fujitsu/a64fx/instruction.json | 131 ++++ .../arch/arm64/fujitsu/a64fx/memory.json | 8 + .../pmu-events/arch/arm64/fujitsu/a64fx/other.json | 188 +++++ .../arch/arm64/fujitsu/a64fx/pipeline.json | 194 +++++ .../pmu-events/arch/arm64/fujitsu/a64fx/sve.json | 110 +++ .../arch/arm64/hisilicon/hip08/metrics.json | 233 ++++++ .../arch/arm64/hisilicon/hip08/uncore-ddrc.json | 58 ++ .../arch/arm64/hisilicon/hip08/uncore-hha.json | 152 ++++ .../arch/arm64/hisilicon/hip08/uncore-l3c.json | 93 +++ .../arch/arm64/hisilicon/hip09/sys/uncore-cpa.json | 81 ++ lib/libpmc/pmu-events/arch/arm64/mapfile.csv | 24 +- lib/libpmc/pmu-events/arch/arm64/recommended.json | 452 ++++++++++++ 168 files changed, 10204 insertions(+), 4 deletions(-) diff --git a/lib/libpmc/pmu-events/arch/arm64/ampere/emag/branch.json b/lib/libpmc/pmu-events/arch/arm64/ampere/emag/branch.json new file mode 100644 index 000000000000..5c69c1e82ef8 --- /dev/null +++ b/lib/libpmc/pmu-events/arch/arm64/ampere/emag/branch.json @@ -0,0 +1,19 @@ +[ + { + "ArchStdEvent": "BR_IMMED_SPEC" + }, + { + "ArchStdEvent": "BR_RETURN_SPEC" + }, + { + "ArchStdEvent": "BR_INDIRECT_SPEC" + }, + { + "ArchStdEvent": "BR_MIS_PRED", + "BriefDescription": "Branch mispredicted" + }, + { + "ArchStdEvent": "BR_PRED", + "BriefDescription": "Predictable branch" + } +] diff --git a/lib/libpmc/pmu-events/arch/arm64/ampere/emag/bus.json b/lib/libpmc/pmu-events/arch/arm64/ampere/emag/bus.json new file mode 100644 index 000000000000..cf48d0dfc759 --- /dev/null +++ b/lib/libpmc/pmu-events/arch/arm64/ampere/emag/bus.json @@ -0,0 +1,23 @@ +[ + { + "ArchStdEvent": "BUS_ACCESS_RD" + }, + { + "ArchStdEvent": "BUS_ACCESS_WR" + }, + { + "ArchStdEvent": "BUS_ACCESS_SHARED" + }, + { + "ArchStdEvent": "BUS_ACCESS_NOT_SHARED" + }, + { + "ArchStdEvent": "BUS_ACCESS_NORMAL" + }, + { + "ArchStdEvent": "BUS_ACCESS_PERIPH" + }, + { + "ArchStdEvent": "BUS_ACCESS" + } +] diff --git a/lib/libpmc/pmu-events/arch/arm64/ampere/emag/cache.json b/lib/libpmc/pmu-events/arch/arm64/ampere/emag/cache.json new file mode 100644 index 000000000000..4cc50b7da526 --- /dev/null +++ b/lib/libpmc/pmu-events/arch/arm64/ampere/emag/cache.json @@ -0,0 +1,161 @@ +[ + { + "ArchStdEvent": "L1D_CACHE_RD" + }, + { + "ArchStdEvent": "L1D_CACHE_WR" + }, + { + "ArchStdEvent": "L1D_CACHE_REFILL_RD" + }, + { + "ArchStdEvent": "L1D_CACHE_INVAL" + }, + { + "ArchStdEvent": "L1D_TLB_REFILL_RD" + }, + { + "ArchStdEvent": "L1D_TLB_REFILL_WR" + }, + { + "ArchStdEvent": "L2D_CACHE_RD" + }, + { + "ArchStdEvent": "L2D_CACHE_WR" + }, + { + "ArchStdEvent": "L2D_CACHE_REFILL_RD" + }, + { + "ArchStdEvent": "L2D_CACHE_REFILL_WR" + }, + { + "ArchStdEvent": "L2D_CACHE_WB_VICTIM" + }, + { + "ArchStdEvent": "L2D_CACHE_WB_CLEAN" + }, + { + "ArchStdEvent": "L2D_CACHE_INVAL" + }, + { + "ArchStdEvent": "L1I_CACHE_REFILL" + }, + { + "ArchStdEvent": "L1I_TLB_REFILL" + }, + { + "ArchStdEvent": "L1D_CACHE_REFILL" + }, + { + "ArchStdEvent": "L1D_CACHE" + }, + { + "ArchStdEvent": "L1D_TLB_REFILL" + }, + { + "ArchStdEvent": "L1I_CACHE" + }, + { + "ArchStdEvent": "L2D_CACHE" + }, + { + "ArchStdEvent": "L2D_CACHE_REFILL" + }, + { + "ArchStdEvent": "L2D_CACHE_WB" + }, + { + "PublicDescription": "This event counts any load or store operation which accesses the data L1 TLB", + "ArchStdEvent": "L1D_TLB", + "BriefDescription": "L1D TLB access" + }, + { + "PublicDescription": "This event counts any instruction fetch which accesses the instruction L1 TLB", + "ArchStdEvent": "L1I_TLB" + }, + { + "PublicDescription": "Level 2 access to data TLB that caused a page table walk. This event counts on any data access which causes L2D_TLB_REFILL to count", + "EventCode": "0x34", + "EventName": "L2D_TLB_ACCESS", + "BriefDescription": "L2D TLB access" + }, + { + "PublicDescription": "Level 2 access to instruciton TLB that caused a page table walk. This event counts on any instruciton access which causes L2I_TLB_REFILL to count", + "EventCode": "0x35", + "EventName": "L2I_TLB_ACCESS", + "BriefDescription": "L2I TLB access" + }, + { + "PublicDescription": "Branch target buffer misprediction", + "EventCode": "0x102", + "EventName": "BTB_MIS_PRED", + "BriefDescription": "BTB misprediction" + }, + { + "PublicDescription": "ITB miss", + "EventCode": "0x103", + "EventName": "ITB_MISS", + "BriefDescription": "ITB miss" + }, + { + "PublicDescription": "DTB miss", + "EventCode": "0x104", + "EventName": "DTB_MISS", + "BriefDescription": "DTB miss" + }, + { + "PublicDescription": "Level 1 data cache late miss", + "EventCode": "0x105", + "EventName": "L1D_CACHE_LATE_MISS", + "BriefDescription": "L1D cache late miss" + }, + { + "PublicDescription": "Level 1 data cache prefetch request", + "EventCode": "0x106", + "EventName": "L1D_CACHE_PREFETCH", + "BriefDescription": "L1D cache prefetch" + }, + { + "PublicDescription": "Level 2 data cache prefetch request", + "EventCode": "0x107", + "EventName": "L2D_CACHE_PREFETCH", + "BriefDescription": "L2D cache prefetch" + }, + { + "PublicDescription": "Level 1 stage 2 TLB refill", + "EventCode": "0x111", + "EventName": "L1_STAGE2_TLB_REFILL", + "BriefDescription": "L1 stage 2 TLB refill" + }, + { + "PublicDescription": "Page walk cache level-0 stage-1 hit", + "EventCode": "0x112", + "EventName": "PAGE_WALK_L0_STAGE1_HIT", + "BriefDescription": "Page walk, L0 stage-1 hit" + }, + { + "PublicDescription": "Page walk cache level-1 stage-1 hit", + "EventCode": "0x113", + "EventName": "PAGE_WALK_L1_STAGE1_HIT", + "BriefDescription": "Page walk, L1 stage-1 hit" + }, + { + "PublicDescription": "Page walk cache level-2 stage-1 hit", + "EventCode": "0x114", + "EventName": "PAGE_WALK_L2_STAGE1_HIT", + "BriefDescription": "Page walk, L2 stage-1 hit" + }, + { + "PublicDescription": "Page walk cache level-1 stage-2 hit", + "EventCode": "0x115", + "EventName": "PAGE_WALK_L1_STAGE2_HIT", + "BriefDescription": "Page walk, L1 stage-2 hit" + }, + { + "PublicDescription": "Page walk cache level-2 stage-2 hit", + "EventCode": "0x116", + "EventName": "PAGE_WALK_L2_STAGE2_HIT", + "BriefDescription": "Page walk, L2 stage-2 hit" + } +] diff --git a/lib/libpmc/pmu-events/arch/arm64/ampere/emag/clock.json b/lib/libpmc/pmu-events/arch/arm64/ampere/emag/clock.json new file mode 100644 index 000000000000..927a6f629a03 --- /dev/null +++ b/lib/libpmc/pmu-events/arch/arm64/ampere/emag/clock.json @@ -0,0 +1,18 @@ +[ + { + "PublicDescription": "The number of core clock cycles", + "ArchStdEvent": "CPU_CYCLES" + }, + { + "PublicDescription": "FSU clocking gated off cycle", + "EventCode": "0x101", + "EventName": "FSU_CLOCK_OFF_CYCLES", + "BriefDescription": "FSU clocking gated off cycle" + }, + { + "PublicDescription": "Wait state cycle", + "EventCode": "0x110", + "EventName": "Wait_CYCLES", + "BriefDescription": "Wait state cycle" + } +] diff --git a/lib/libpmc/pmu-events/arch/arm64/ampere/emag/exception.json b/lib/libpmc/pmu-events/arch/arm64/ampere/emag/exception.json new file mode 100644 index 000000000000..ada052e19632 --- /dev/null +++ b/lib/libpmc/pmu-events/arch/arm64/ampere/emag/exception.json @@ -0,0 +1,44 @@ +[ + { + "ArchStdEvent": "EXC_UNDEF" + }, + { + "ArchStdEvent": "EXC_SVC" + }, + { + "ArchStdEvent": "EXC_PABORT" + }, + { + "ArchStdEvent": "EXC_DABORT" + }, + { + "ArchStdEvent": "EXC_IRQ" + }, + { + "ArchStdEvent": "EXC_FIQ" + }, + { + "ArchStdEvent": "EXC_HVC" + }, + { + "ArchStdEvent": "EXC_TRAP_PABORT" + }, + { + "ArchStdEvent": "EXC_TRAP_DABORT" + }, + { + "ArchStdEvent": "EXC_TRAP_OTHER" + }, + { + "ArchStdEvent": "EXC_TRAP_IRQ" + }, + { + "ArchStdEvent": "EXC_TRAP_FIQ" + }, + { + "ArchStdEvent": "EXC_TAKEN" + }, + { + "ArchStdEvent": "EXC_RETURN" + } +] diff --git a/lib/libpmc/pmu-events/arch/arm64/ampere/emag/instruction.json b/lib/libpmc/pmu-events/arch/arm64/ampere/emag/instruction.json new file mode 100644 index 000000000000..62f6276e3016 --- /dev/null +++ b/lib/libpmc/pmu-events/arch/arm64/ampere/emag/instruction.json @@ -0,0 +1,73 @@ +[ + { + "ArchStdEvent": "LD_SPEC" + }, + { + "ArchStdEvent": "ST_SPEC" + }, + { + "ArchStdEvent": "LDST_SPEC" + }, + { + "ArchStdEvent": "DP_SPEC" + }, + { + "ArchStdEvent": "ASE_SPEC" + }, + { + "ArchStdEvent": "VFP_SPEC" + }, + { + "ArchStdEvent": "PC_WRITE_SPEC" + }, + { + "ArchStdEvent": "CRYPTO_SPEC" + }, + { + "ArchStdEvent": "ISB_SPEC" + }, + { + "ArchStdEvent": "DSB_SPEC" + }, + { + "ArchStdEvent": "DMB_SPEC" + }, + { + "ArchStdEvent": "RC_LD_SPEC" + }, + { + "ArchStdEvent": "RC_ST_SPEC" + }, + { + "PublicDescription": "Instruction architecturally executed, software increment", + "ArchStdEvent": "SW_INCR", + "BriefDescription": "Software increment" + }, + { + "ArchStdEvent": "INST_RETIRED" + }, + { + "ArchStdEvent": "CID_WRITE_RETIRED", + "BriefDescription": "Write to CONTEXTIDR" + }, + { + "ArchStdEvent": "INST_SPEC" + }, + { + "ArchStdEvent": "TTBR_WRITE_RETIRED" + }, + { + "PublicDescription": "This event counts all branches, taken or not. This excludes exception entries, debug entries and CCFAIL branches", + "ArchStdEvent": "BR_RETIRED" + }, + { + "PublicDescription": "This event counts any branch counted by BR_RETIRED which is not correctly predicted and causes a pipeline flush", + "ArchStdEvent": "BR_MIS_PRED_RETIRED" + }, + { + "PublicDescription": "Operation speculatively executed, NOP", + "EventCode": "0x100", + "EventName": "NOP_SPEC", + "BriefDescription": "Speculatively executed, NOP" + } +] diff --git a/lib/libpmc/pmu-events/arch/arm64/ampere/emag/intrinsic.json b/lib/libpmc/pmu-events/arch/arm64/ampere/emag/intrinsic.json new file mode 100644 index 000000000000..7ecffb989ae0 --- /dev/null +++ b/lib/libpmc/pmu-events/arch/arm64/ampere/emag/intrinsic.json @@ -0,0 +1,14 @@ +[ + { + "ArchStdEvent": "LDREX_SPEC" + }, + { + "ArchStdEvent": "STREX_PASS_SPEC" + }, + { + "ArchStdEvent": "STREX_FAIL_SPEC" + }, + { + "ArchStdEvent": "STREX_SPEC" + } +] diff --git a/lib/libpmc/pmu-events/arch/arm64/ampere/emag/memory.json b/lib/libpmc/pmu-events/arch/arm64/ampere/emag/memory.json new file mode 100644 index 000000000000..50157e8c2005 --- /dev/null +++ b/lib/libpmc/pmu-events/arch/arm64/ampere/emag/memory.json @@ -0,0 +1,24 @@ +[ + { + "ArchStdEvent": "MEM_ACCESS_RD" + }, + { + "ArchStdEvent": "MEM_ACCESS_WR" + }, + { + "ArchStdEvent": "UNALIGNED_LD_SPEC" + }, + { + "ArchStdEvent": "UNALIGNED_ST_SPEC" + }, + { + "ArchStdEvent": "UNALIGNED_LDST_SPEC" + }, + { + "ArchStdEvent": "MEM_ACCESS" + }, + { + "PublicDescription": "This event counts any correctable or uncorrectable memory error (ECC or parity) in the protected core RAMs", + "ArchStdEvent": "MEMORY_ERROR" + } +] diff --git a/lib/libpmc/pmu-events/arch/arm64/ampere/emag/pipeline.json b/lib/libpmc/pmu-events/arch/arm64/ampere/emag/pipeline.json new file mode 100644 index 000000000000..17c71aba6612 --- /dev/null +++ b/lib/libpmc/pmu-events/arch/arm64/ampere/emag/pipeline.json @@ -0,0 +1,50 @@ +[ + { + "PublicDescription": "Decode starved for instruction cycle", + "EventCode": "0x108", + "EventName": "DECODE_STALL", + "BriefDescription": "Decode starved" + }, + { + "PublicDescription": "Op dispatch stalled cycle", + "EventCode": "0x109", + "EventName": "DISPATCH_STALL", + "BriefDescription": "Dispatch stalled" + }, + { + "PublicDescription": "IXA Op non-issue", + "EventCode": "0x10a", + "EventName": "IXA_STALL", + "BriefDescription": "IXA stalled" + }, + { + "PublicDescription": "IXB Op non-issue", + "EventCode": "0x10b", + "EventName": "IXB_STALL", + "BriefDescription": "IXB stalled" + }, + { + "PublicDescription": "BX Op non-issue", + "EventCode": "0x10c", + "EventName": "BX_STALL", + "BriefDescription": "BX stalled" + }, + { + "PublicDescription": "LX Op non-issue", + "EventCode": "0x10d", + "EventName": "LX_STALL", + "BriefDescription": "LX stalled" + }, + { + "PublicDescription": "SX Op non-issue", + "EventCode": "0x10e", + "EventName": "SX_STALL", + "BriefDescription": "SX stalled" + }, + { + "PublicDescription": "FX Op non-issue", + "EventCode": "0x10f", + "EventName": "FX_STALL", + "BriefDescription": "FX stalled" + } +] diff --git a/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a34/branch.json b/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a34/branch.json new file mode 100644 index 000000000000..ece201718284 --- /dev/null +++ b/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a34/branch.json @@ -0,0 +1,11 @@ +[ + { + "ArchStdEvent": "BR_MIS_PRED" + }, + { + "ArchStdEvent": "BR_PRED" + }, + { + "ArchStdEvent": "BR_INDIRECT_SPEC" + } +] diff --git a/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a34/bus.json b/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a34/bus.json new file mode 100644 index 000000000000..75d850b781ac --- /dev/null +++ b/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a34/bus.json @@ -0,0 +1,17 @@ +[ + { + "ArchStdEvent": "CPU_CYCLES" + }, + { + "ArchStdEvent": "BUS_ACCESS" + }, + { + "ArchStdEvent": "BUS_CYCLES" + }, + { + "ArchStdEvent": "BUS_ACCESS_RD" + }, + { + "ArchStdEvent": "BUS_ACCESS_WR" + } +] diff --git a/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a34/cache.json b/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a34/cache.json new file mode 100644 index 000000000000..8a9a95e05c32 --- /dev/null +++ b/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a34/cache.json @@ -0,0 +1,32 @@ +[ + { + "ArchStdEvent": "L1I_CACHE_REFILL" + }, + { + "ArchStdEvent": "L1I_TLB_REFILL" + }, + { + "ArchStdEvent": "L1D_CACHE_REFILL" + }, + { + "ArchStdEvent": "L1D_CACHE" + }, + { + "ArchStdEvent": "L1D_TLB_REFILL" + }, + { + "ArchStdEvent": "L1I_CACHE" + }, + { + "ArchStdEvent": "L1D_CACHE_WB" + }, + { + "ArchStdEvent": "L2D_CACHE" + }, + { + "ArchStdEvent": "L2D_CACHE_REFILL" + }, + { + "ArchStdEvent": "L2D_CACHE_WB" + } +] diff --git a/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a34/exception.json b/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a34/exception.json new file mode 100644 index 000000000000..27c3fe9c831a --- /dev/null +++ b/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a34/exception.json @@ -0,0 +1,14 @@ +[ + { + "ArchStdEvent": "EXC_TAKEN" + }, + { + "ArchStdEvent": "MEMORY_ERROR" + }, + { + "ArchStdEvent": "EXC_IRQ" + }, + { + "ArchStdEvent": "EXC_FIQ" + } +] diff --git a/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a34/instruction.json b/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a34/instruction.json new file mode 100644 index 000000000000..7c018f439206 --- /dev/null +++ b/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a34/instruction.json @@ -0,0 +1,29 @@ +[ + { + "ArchStdEvent": "SW_INCR" + }, + { + "ArchStdEvent": "LD_RETIRED" + }, + { + "ArchStdEvent": "ST_RETIRED" + }, + { + "ArchStdEvent": "INST_RETIRED" + }, + { + "ArchStdEvent": "EXC_RETURN" + }, + { + "ArchStdEvent": "CID_WRITE_RETIRED" + }, + { + "ArchStdEvent": "PC_WRITE_RETIRED" + }, + { + "ArchStdEvent": "BR_IMMED_RETIRED" + }, + { + "ArchStdEvent": "BR_RETURN_RETIRED" + } +] diff --git a/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a34/memory.json b/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a34/memory.json new file mode 100644 index 000000000000..2c319f936957 --- /dev/null +++ b/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a34/memory.json @@ -0,0 +1,8 @@ +[ + { + "ArchStdEvent": "UNALIGNED_LDST_RETIRED" + }, + { + "ArchStdEvent": "MEM_ACCESS" + } +] diff --git a/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a35/branch.json b/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a35/branch.json new file mode 100644 index 000000000000..ece201718284 --- /dev/null +++ b/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a35/branch.json @@ -0,0 +1,11 @@ +[ + { + "ArchStdEvent": "BR_MIS_PRED" + }, + { + "ArchStdEvent": "BR_PRED" + }, + { + "ArchStdEvent": "BR_INDIRECT_SPEC" + } +] diff --git a/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a35/bus.json b/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a35/bus.json new file mode 100644 index 000000000000..75d850b781ac --- /dev/null +++ b/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a35/bus.json @@ -0,0 +1,17 @@ +[ + { + "ArchStdEvent": "CPU_CYCLES" + }, + { + "ArchStdEvent": "BUS_ACCESS" + }, + { + "ArchStdEvent": "BUS_CYCLES" + }, + { + "ArchStdEvent": "BUS_ACCESS_RD" + }, + { + "ArchStdEvent": "BUS_ACCESS_WR" + } +] diff --git a/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a35/cache.json b/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a35/cache.json new file mode 100644 index 000000000000..8a9a95e05c32 --- /dev/null +++ b/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a35/cache.json @@ -0,0 +1,32 @@ +[ + { + "ArchStdEvent": "L1I_CACHE_REFILL" + }, + { + "ArchStdEvent": "L1I_TLB_REFILL" + }, + { + "ArchStdEvent": "L1D_CACHE_REFILL" + }, + { + "ArchStdEvent": "L1D_CACHE" + }, + { + "ArchStdEvent": "L1D_TLB_REFILL" + }, + { + "ArchStdEvent": "L1I_CACHE" + }, + { + "ArchStdEvent": "L1D_CACHE_WB" + }, + { + "ArchStdEvent": "L2D_CACHE" + }, + { + "ArchStdEvent": "L2D_CACHE_REFILL" + }, + { + "ArchStdEvent": "L2D_CACHE_WB" + } +] diff --git a/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a35/exception.json b/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a35/exception.json new file mode 100644 index 000000000000..27c3fe9c831a --- /dev/null +++ b/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a35/exception.json @@ -0,0 +1,14 @@ +[ + { + "ArchStdEvent": "EXC_TAKEN" + }, + { + "ArchStdEvent": "MEMORY_ERROR" + }, + { + "ArchStdEvent": "EXC_IRQ" + }, + { + "ArchStdEvent": "EXC_FIQ" + } +] diff --git a/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a35/instruction.json b/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a35/instruction.json new file mode 100644 index 000000000000..df9f94cfc8d5 --- /dev/null +++ b/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a35/instruction.json @@ -0,0 +1,44 @@ +[ + { + "ArchStdEvent": "SW_INCR" + }, + { + "ArchStdEvent": "LD_RETIRED" + }, + { + "ArchStdEvent": "ST_RETIRED" + }, + { + "ArchStdEvent": "INST_RETIRED" + }, + { + "ArchStdEvent": "EXC_RETURN" + }, + { + "ArchStdEvent": "CID_WRITE_RETIRED" + }, + { + "ArchStdEvent": "PC_WRITE_RETIRED" + }, + { + "ArchStdEvent": "BR_IMMED_RETIRED" + }, + { + "ArchStdEvent": "BR_RETURN_RETIRED" + }, + { + "ArchStdEvent": "INST_SPEC" + }, + { + "ArchStdEvent": "DP_SPEC" + }, + { + "ArchStdEvent": "ASE_SPEC" + }, + { + "ArchStdEvent": "VFP_SPEC" + }, + { + "ArchStdEvent": "CRYPTO_SPEC" + } +] diff --git a/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a35/memory.json b/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a35/memory.json new file mode 100644 index 000000000000..2c319f936957 --- /dev/null +++ b/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a35/memory.json @@ -0,0 +1,8 @@ +[ + { + "ArchStdEvent": "UNALIGNED_LDST_RETIRED" + }, + { + "ArchStdEvent": "MEM_ACCESS" + } +] diff --git a/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a510/branch.json b/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a510/branch.json new file mode 100644 index 000000000000..411fcbdbd7e6 --- /dev/null +++ b/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a510/branch.json *** 10440 LINES SKIPPED ***