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Date:      Wed, 14 Nov 2018 14:26:32 +0000 (UTC)
From:      Luiz Otavio O Souza <loos@FreeBSD.org>
To:        src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org
Subject:   svn commit: r340432 - in head/sys/arm: conf mv
Message-ID:  <201811141426.wAEEQWoK041437@repo.freebsd.org>

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Author: loos
Date: Wed Nov 14 14:26:32 2018
New Revision: 340432
URL: https://svnweb.freebsd.org/changeset/base/340432

Log:
  Add the driver for the SPI controller on ARMADA38X.
  
  Tested on Clearfog (Pro) and SG-3100.
  
  Sponsored by:	Rubicon Communications, LLC (Netgate)

Added:
  head/sys/arm/mv/mv_spi.c   (contents, props changed)
Modified:
  head/sys/arm/conf/ARMADA38X
  head/sys/arm/conf/GENERIC
  head/sys/arm/mv/files.arm7

Modified: head/sys/arm/conf/ARMADA38X
==============================================================================
--- head/sys/arm/conf/ARMADA38X	Wed Nov 14 14:18:35 2018	(r340431)
+++ head/sys/arm/conf/ARMADA38X	Wed Nov 14 14:26:32 2018	(r340432)
@@ -76,6 +76,11 @@ device		iic
 device		iicbus
 device		twsi
 
+# SPI
+device		spibus
+device		spigen
+device		mv_spi
+
 # Wireless NIC cards
 device		wlan		# 802.11 support
 device		ath		# Atheros NIC's

Modified: head/sys/arm/conf/GENERIC
==============================================================================
--- head/sys/arm/conf/GENERIC	Wed Nov 14 14:18:35 2018	(r340431)
+++ head/sys/arm/conf/GENERIC	Wed Nov 14 14:26:32 2018	(r340432)
@@ -169,6 +169,7 @@ device		aw_cir
 device		spibus
 device		spigen
 device		bcm2835_spi
+device		mv_spi
 device		ti_spi
 
 # ADC support

Modified: head/sys/arm/mv/files.arm7
==============================================================================
--- head/sys/arm/mv/files.arm7	Wed Nov 14 14:18:35 2018	(r340431)
+++ head/sys/arm/mv/files.arm7	Wed Nov 14 14:26:32 2018	(r340432)
@@ -18,6 +18,7 @@ arm/mv/armada38x/armada38x_mp.c	optional	smp
 arm/mv/armada38x/pmsu.c		standard
 arm/mv/armada38x/armada38x_rtc.c		standard
 arm/mv/armada38x/armada38x_pl310.c	optional pl310
+arm/mv/mv_spi.c			optional	mv_spi spibus
 dev/sdhci/sdhci_fdt.c		optional	sdhci
 
 arm/mv/rtc.c			standard

Added: head/sys/arm/mv/mv_spi.c
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ head/sys/arm/mv/mv_spi.c	Wed Nov 14 14:26:32 2018	(r340432)
@@ -0,0 +1,351 @@
+/*-
+ * Copyright (c) 2017-2018, Rubicon Communications, LLC (Netgate)
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <sys/rman.h>
+
+#include <machine/bus.h>
+#include <machine/resource.h>
+#include <machine/intr.h>
+
+#include <dev/ofw/ofw_bus.h>
+#include <dev/ofw/ofw_bus_subr.h>
+#include <dev/spibus/spi.h>
+#include <dev/spibus/spibusvar.h>
+
+#include "spibus_if.h"
+
+struct mv_spi_softc {
+	device_t		sc_dev;
+	struct mtx		sc_mtx;
+	struct resource		*sc_mem_res;
+	struct resource		*sc_irq_res;
+	struct spi_command	*sc_cmd;
+	bus_space_tag_t		sc_bst;
+	bus_space_handle_t	sc_bsh;
+	uint32_t		sc_len;
+	uint32_t		sc_read;
+	uint32_t		sc_flags;
+	uint32_t		sc_written;
+	void			*sc_intrhand;
+};
+
+#define	MV_SPI_BUSY		0x1
+#define	MV_SPI_WRITE(_sc, _off, _val)		\
+    bus_space_write_4((_sc)->sc_bst, (_sc)->sc_bsh, (_off), (_val))
+#define	MV_SPI_READ(_sc, _off)			\
+    bus_space_read_4((_sc)->sc_bst, (_sc)->sc_bsh, (_off))
+#define	MV_SPI_LOCK(_sc)	mtx_lock(&(_sc)->sc_mtx)
+#define	MV_SPI_UNLOCK(_sc)	mtx_unlock(&(_sc)->sc_mtx)
+
+#define	MV_SPI_CONTROL		0
+#define	MV_SPI_CTRL_CS_SHIFT		2
+#define	MV_SPI_CTRL_SMEMREADY		(1 << 1)
+#define	MV_SPI_CTRL_CS_ACTIVE		(1 << 0)
+#define	MV_SPI_CONF		0x4
+#define	MV_SPI_CONF_BYTELEN		(1 << 5)
+#define	MV_SPI_DATAOUT		0x8
+#define	MV_SPI_DATAIN		0xc
+#define	MV_SPI_INTR_STAT	0x10
+#define	MV_SPI_INTR_MASK	0x14
+#define	MV_SPI_INTR_SMEMREADY		(1 << 0)
+
+static struct ofw_compat_data compat_data[] = {
+        {"marvell,armada-380-spi",	1},
+        {NULL,                          0}
+};
+
+static void mv_spi_intr(void *);
+
+static int
+mv_spi_probe(device_t dev)
+{
+
+	if (!ofw_bus_status_okay(dev))
+		return (ENXIO);
+	if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
+		return (ENXIO);
+
+	device_set_desc(dev, "Marvell SPI controller");
+
+	return (BUS_PROBE_DEFAULT);
+}
+
+static int
+mv_spi_attach(device_t dev)
+{
+	struct mv_spi_softc *sc;
+	int rid;
+	uint32_t reg;
+
+	sc = device_get_softc(dev);
+	sc->sc_dev = dev;
+
+	rid = 0;
+	sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
+	    RF_ACTIVE);
+	if (!sc->sc_mem_res) {
+		device_printf(dev, "cannot allocate memory window\n");
+		return (ENXIO);
+	}
+
+	sc->sc_bst = rman_get_bustag(sc->sc_mem_res);
+	sc->sc_bsh = rman_get_bushandle(sc->sc_mem_res);
+
+	rid = 0;
+	sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
+	    RF_ACTIVE);
+	if (!sc->sc_irq_res) {
+		bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
+		device_printf(dev, "cannot allocate interrupt\n");
+		return (ENXIO);
+	}
+
+	/* Deactivate the bus - just in case... */
+	reg = MV_SPI_READ(sc, MV_SPI_CONTROL);
+	MV_SPI_WRITE(sc, MV_SPI_CONTROL, reg & ~MV_SPI_CTRL_CS_ACTIVE);
+
+	/* Disable the two bytes FIFO. */
+	reg = MV_SPI_READ(sc, MV_SPI_CONF);
+	MV_SPI_WRITE(sc, MV_SPI_CONF, reg & ~MV_SPI_CONF_BYTELEN);
+
+	/* Clear and disable interrupts. */
+	MV_SPI_WRITE(sc, MV_SPI_INTR_MASK, 0);
+	MV_SPI_WRITE(sc, MV_SPI_INTR_STAT, 0);
+
+	/* Hook up our interrupt handler. */
+	if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
+	    NULL, mv_spi_intr, sc, &sc->sc_intrhand)) {
+		bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
+		bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
+		device_printf(dev, "cannot setup the interrupt handler\n");
+		return (ENXIO);
+	}
+
+	mtx_init(&sc->sc_mtx, "mv_spi", NULL, MTX_DEF);
+
+	device_add_child(dev, "spibus", -1);
+
+	/* Probe and attach the spibus when interrupts are available. */
+	config_intrhook_oneshot((ich_func_t)bus_generic_attach, dev);
+
+	return (0);
+}
+
+static int
+mv_spi_detach(device_t dev)
+{
+	struct mv_spi_softc *sc;
+
+	bus_generic_detach(dev);
+
+	sc = device_get_softc(dev);
+	mtx_destroy(&sc->sc_mtx);
+	if (sc->sc_intrhand)
+		bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intrhand);
+	if (sc->sc_irq_res)
+		bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
+	if (sc->sc_mem_res)
+		bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
+
+	return (0);
+}
+
+static __inline void
+mv_spi_rx_byte(struct mv_spi_softc *sc)
+{
+	struct spi_command *cmd;
+	uint32_t read;
+	uint8_t *p;
+
+	cmd = sc->sc_cmd; 
+	p = (uint8_t *)cmd->rx_cmd;
+	read = sc->sc_read++;
+	if (read >= cmd->rx_cmd_sz) {
+		p = (uint8_t *)cmd->rx_data;
+		read -= cmd->rx_cmd_sz;
+	}
+	p[read] = MV_SPI_READ(sc, MV_SPI_DATAIN) & 0xff;
+}
+
+static __inline void
+mv_spi_tx_byte(struct mv_spi_softc *sc)
+{
+	struct spi_command *cmd;
+	uint32_t written;
+	uint8_t *p;
+
+	cmd = sc->sc_cmd; 
+	p = (uint8_t *)cmd->tx_cmd;
+	written = sc->sc_written++;
+	if (written >= cmd->tx_cmd_sz) {
+		p = (uint8_t *)cmd->tx_data;
+		written -= cmd->tx_cmd_sz;
+	}
+	MV_SPI_WRITE(sc, MV_SPI_DATAOUT, p[written]);
+}
+
+static void
+mv_spi_intr(void *arg)
+{
+	struct mv_spi_softc *sc;
+
+	sc = (struct mv_spi_softc *)arg;
+	MV_SPI_LOCK(sc);
+
+	/* Filter stray interrupts. */
+	if ((sc->sc_flags & MV_SPI_BUSY) == 0) {
+		MV_SPI_UNLOCK(sc);
+		return;
+	}
+
+	/* RX */
+	mv_spi_rx_byte(sc);
+
+	/* TX */
+	mv_spi_tx_byte(sc);
+
+	/* Check for end of transfer. */
+	if (sc->sc_written == sc->sc_len && sc->sc_read == sc->sc_len)
+		wakeup(sc->sc_dev);
+
+	MV_SPI_UNLOCK(sc);
+}
+
+static int
+mv_spi_transfer(device_t dev, device_t child, struct spi_command *cmd)
+{
+	struct mv_spi_softc *sc;
+	uint32_t cs, reg;
+	int resid, timeout;
+
+	KASSERT(cmd->tx_cmd_sz == cmd->rx_cmd_sz,
+	    ("TX/RX command sizes should be equal"));
+	KASSERT(cmd->tx_data_sz == cmd->rx_data_sz,
+	    ("TX/RX data sizes should be equal"));
+
+	/* Get the proper chip select for this child. */
+	spibus_get_cs(child, &cs);
+	cs &= ~SPIBUS_CS_HIGH;
+
+	sc = device_get_softc(dev);
+	MV_SPI_LOCK(sc);
+
+	/* Wait until the controller is free. */
+	while (sc->sc_flags & MV_SPI_BUSY)
+		mtx_sleep(dev, &sc->sc_mtx, 0, "mv_spi", 0);
+
+	/* Now we have control over SPI controller. */
+	sc->sc_flags = MV_SPI_BUSY;
+
+	/* Save a pointer to the SPI command. */
+	sc->sc_cmd = cmd;
+	sc->sc_read = 0;
+	sc->sc_written = 0;
+	sc->sc_len = cmd->tx_cmd_sz + cmd->tx_data_sz;
+
+	MV_SPI_WRITE(sc, MV_SPI_CONTROL, cs << MV_SPI_CTRL_CS_SHIFT);
+	reg = MV_SPI_READ(sc, MV_SPI_CONTROL);
+	MV_SPI_WRITE(sc, MV_SPI_CONTROL, reg | MV_SPI_CTRL_CS_ACTIVE);
+
+	while ((resid = sc->sc_len - sc->sc_written) > 0) {
+
+		MV_SPI_WRITE(sc, MV_SPI_INTR_STAT, 0);
+
+		/*
+		 * Write to start the transmission and read the byte
+		 * back when ready.
+		 */
+		mv_spi_tx_byte(sc);
+		timeout = 1000;
+		while (--timeout > 0) {
+			reg = MV_SPI_READ(sc, MV_SPI_CONTROL);
+			if (reg & MV_SPI_CTRL_SMEMREADY)
+				break;
+			DELAY(1);
+		}
+		if (timeout == 0)
+			break;
+		mv_spi_rx_byte(sc);
+	}
+
+	/* Stop the controller. */
+	reg = MV_SPI_READ(sc, MV_SPI_CONTROL);
+	MV_SPI_WRITE(sc, MV_SPI_CONTROL, reg & ~MV_SPI_CTRL_CS_ACTIVE);
+	MV_SPI_WRITE(sc, MV_SPI_INTR_MASK, 0);
+	MV_SPI_WRITE(sc, MV_SPI_INTR_STAT, 0);
+
+	/* Release the controller and wakeup the next thread waiting for it. */
+	sc->sc_flags = 0;
+	wakeup_one(dev);
+	MV_SPI_UNLOCK(sc);
+
+	/*
+	 * Check for transfer timeout.  The SPI controller doesn't
+	 * return errors.
+	 */
+	return ((timeout == 0) ? EIO : 0);
+}
+
+static phandle_t
+mv_spi_get_node(device_t bus, device_t dev)
+{
+
+	return (ofw_bus_get_node(bus));
+}
+
+static device_method_t mv_spi_methods[] = {
+	/* Device interface */
+	DEVMETHOD(device_probe,		mv_spi_probe),
+	DEVMETHOD(device_attach,	mv_spi_attach),
+	DEVMETHOD(device_detach,	mv_spi_detach),
+
+	/* SPI interface */
+	DEVMETHOD(spibus_transfer,	mv_spi_transfer),
+
+	/* ofw_bus interface */
+	DEVMETHOD(ofw_bus_get_node,	mv_spi_get_node),
+
+	DEVMETHOD_END
+};
+
+static devclass_t mv_spi_devclass;
+
+static driver_t mv_spi_driver = {
+	"spi",
+	mv_spi_methods,
+	sizeof(struct mv_spi_softc),
+};
+
+DRIVER_MODULE(mv_spi, simplebus, mv_spi_driver, mv_spi_devclass, 0, 0);



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