From owner-freebsd-hardware Fri Sep 12 11:25:43 1997 Return-Path: Received: (from root@localhost) by hub.freebsd.org (8.8.7/8.8.7) id LAA26022 for hardware-outgoing; Fri, 12 Sep 1997 11:25:43 -0700 (PDT) Received: from lariat.lariat.org (ppp0.lariat.org@[129.72.251.2]) by hub.freebsd.org (8.8.7/8.8.7) with ESMTP id LAA26013 for ; Fri, 12 Sep 1997 11:25:38 -0700 (PDT) Received: from solo ([129.72.251.10] (may be forged)) by lariat.lariat.org (8.8.6/8.8.6) with SMTP id MAA27857; Fri, 12 Sep 1997 12:21:08 -0600 (MDT) Message-Id: <3.0.3.32.19970912122501.009588b0@mail.lariat.org> X-Sender: brett@mail.lariat.org X-Mailer: QUALCOMM Windows Eudora Pro Version 3.0.3 (32) Date: Fri, 12 Sep 1997 12:25:01 -0600 To: roberto@keltia.freenix.fr, freebsd-hardware@FreeBSD.ORG From: Brett Glass Subject: Re: IBM/Cyrix PR200+ In-Reply-To: <88256510.00608242.00@IWNS2.infoworld.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Sender: owner-freebsd-hardware@FreeBSD.ORG X-Loop: FreeBSD.org Precedence: bulk If the FPU attempts to normalize or convert the number, or otherwise do something with the remaining 16 bits of the 80-bit internal register, it might be slower. I've wondered about this but haven't tested yet. --Brett Glass At 07:58 AM 9/12/97 +0200, roberto@keltia.freenix.fr wrote: >I don't expect it to be faster with the MMX registers because they're >shared with the FPU ones... (like the Intel MMX registers). I've not made >any test though. >-- >Ollivier ROBERT -=- FreeBSD: There are no limits -=- >roberto@keltia.freenix.fr >FreeBSD keltia.freenix.fr 3.0-CURRENT #31: Sat Sep 6 21:58:17 CEST 1997 > > > >