From nobody Tue Jan 13 16:27:34 2026 X-Original-To: dev-commits-src-all@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id 4drF5f6pXkz6NN0K for ; Tue, 13 Jan 2026 16:27:34 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "R13" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 4drF5f2C8qz3L18 for ; Tue, 13 Jan 2026 16:27:34 +0000 (UTC) (envelope-from git@FreeBSD.org) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1768321654; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=/Wze2Lk31WkWxSZiHyMxpwUD+qdco05n031JBhOpN50=; b=CMqU5Sw8rKhEEXvKXPDfBBiONbbawHppHk6zdw9y9V98Lbm7mNaDnXRIi+b1eGJoA36vOa EiLGegwoF1N0aYvBF4FLfMzpQgqHjrsTj906Q7x3xDmUMNT8XILY4h045+hRpb7ui7zC4g TeKYiMBihxNHplQJ3in22ihOrZRAceSIxDd6+x3CEi8ZowTtVStQ58zdLwaqlkOJvGIfYm u773vlyDx6b4pLBmyOLKoBRiAfLthRZ4V6TnorLcGwonPUnsu+xniJcwYQlIxskwF42On7 YPr0lvunehoGOIRvXzwp/qxPbQyGUNzIM4KFyuEbWxng8k3F3BJ3otPHF6Q/Zg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1768321654; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=/Wze2Lk31WkWxSZiHyMxpwUD+qdco05n031JBhOpN50=; b=du9UdEnClkwUrManKgic50VvYyoj20xOez9cAk59eX0k0Ubgc4BzlKB1L1KR+l6xroIa+Y qvOdSjCo0X4iqUof/2QIyD7Y+Uz/PPOqoj2Rhnf73Ci2IrLF2O/9kwPUT8e1ifDAtey9dP j/kw/yFsyoUSCoheMF2SKJsAUZU34m9rc2XwrX385WUdQmVWuwugfntdzvYolfz256xBvG 1LJLgZeTAZlCMIgp9DRmsWFQ25OeEgX77OH7YxLLhr+85g8Umkq237qEcBPP2sq0Watl0M VyLl2ZjX8Z0C+fUu+qhqeddfhWjrNx8lKNfptCtA8TmsSs3+n/BmtKZiUAj0mg== ARC-Seal: i=1; s=dkim; d=freebsd.org; t=1768321654; a=rsa-sha256; cv=none; b=kS8UVS9SdKA+duJiu4Q7TqnCz0rWVUsTjRQrJmk8FjQM0a+3+le3Yn1wolW47BfkaJSkgp LK8aySfq/BzoRt1HlrUpUPLMxBUoScc6PMsU3kPoTx35ZTdysrzfOw0cQML3FlzSibkdh4 axPb0YUTgi4+idrzyMortEIr/rVntOsgJ3S7uZm2mg/bGnvEPoL7/NHTexTtvgYikr5QFB 5tO0fvpWB1tz2pOQIWbau4Z3MPt7LaMEH2RvMLIN4132KVUOiRatD1ucDMQDLbUF8XOp4M odHCalCLlt0ET0/JUvnQcvPlTU8PAkLTpyS7XxVttfZSoYEjnmu+sU4xDDDwDA== ARC-Authentication-Results: i=1; mx1.freebsd.org; none Received: from gitrepo.freebsd.org (gitrepo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:5]) by mxrelay.nyi.freebsd.org (Postfix) with ESMTP id 4drF5f1ZsQz4ch for ; Tue, 13 Jan 2026 16:27:34 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from git (uid 1279) (envelope-from git@FreeBSD.org) id 30949 by gitrepo.freebsd.org (DragonFly Mail Agent v0.13+ on gitrepo.freebsd.org); Tue, 13 Jan 2026 16:27:34 +0000 To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-branches@FreeBSD.org From: Andrew Turner Subject: git: bbd57dcdeed7 - stable/15 - arm64: Split out accessing special registers List-Id: Commit messages for all branches of the src repository List-Archive: https://lists.freebsd.org/archives/dev-commits-src-all List-Help: List-Post: List-Subscribe: List-Unsubscribe: X-BeenThere: dev-commits-src-all@freebsd.org Sender: owner-dev-commits-src-all@FreeBSD.org MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Git-Committer: andrew X-Git-Repository: src X-Git-Refname: refs/heads/stable/15 X-Git-Reftype: branch X-Git-Commit: bbd57dcdeed7d524252f0680a5f0c3752d8a203b Auto-Submitted: auto-generated Date: Tue, 13 Jan 2026 16:27:34 +0000 Message-Id: <69667276.30949.23f2f8e4@gitrepo.freebsd.org> The branch stable/15 has been updated by andrew: URL: https://cgit.FreeBSD.org/src/commit/?id=bbd57dcdeed7d524252f0680a5f0c3752d8a203b commit bbd57dcdeed7d524252f0680a5f0c3752d8a203b Author: Andrew Turner AuthorDate: 2025-10-27 10:56:17 +0000 Commit: Andrew Turner CommitDate: 2026-01-13 14:06:20 +0000 arm64: Split out accessing special registers We shouldn't need to include armreg.h just to access special registers that are not defined in this file. Split out the parts that should be common with arm64.h and hypervisor.h. Reviewed by: emaste Sponsored by: Arm Ltd Differential Revision: https://reviews.freebsd.org/D53324 (cherry picked from commit b57a571a001958febec042e15c571c5074ce44ce) --- sys/arm64/include/_armreg.h | 56 ++++++++++++++++++++++++++++++++++++++++++ sys/arm64/include/armreg.h | 20 ++------------- sys/arm64/include/hypervisor.h | 2 ++ 3 files changed, 60 insertions(+), 18 deletions(-) diff --git a/sys/arm64/include/_armreg.h b/sys/arm64/include/_armreg.h new file mode 100644 index 000000000000..7aa3c358b327 --- /dev/null +++ b/sys/arm64/include/_armreg.h @@ -0,0 +1,56 @@ +/*- + * Copyright (c) 2013, 2014 Andrew Turner + * Copyright (c) 2015,2021 The FreeBSD Foundation + * + * Portions of this software were developed by Andrew Turner + * under sponsorship from the FreeBSD Foundation. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#if !defined(_MACHINE_ARMREG_H_) && \ + !defined(_MACHINE_HYPERVISOR_H_) +#error Do not include this file directly +#endif + +#ifndef _MACHINE__ARMREG_H_ +#define _MACHINE__ARMREG_H_ + +#define __MRS_REG_ALT_NAME(op0, op1, crn, crm, op2) \ + S##op0##_##op1##_C##crn##_C##crm##_##op2 +#define _MRS_REG_ALT_NAME(op0, op1, crn, crm, op2) \ + __MRS_REG_ALT_NAME(op0, op1, crn, crm, op2) +#define MRS_REG_ALT_NAME(reg) \ + _MRS_REG_ALT_NAME(reg##_op0, reg##_op1, reg##_CRn, reg##_CRm, reg##_op2) + + +#define READ_SPECIALREG(reg) \ +({ uint64_t _val; \ + __asm __volatile("mrs %0, " __STRING(reg) : "=&r" (_val)); \ + _val; \ +}) +#define WRITE_SPECIALREG(reg, _val) \ + __asm __volatile("msr " __STRING(reg) ", %0" : : "r"((uint64_t)_val)) + +#define UL(x) UINT64_C(x) + +#endif /* !_MACHINE__ARMREG_H_ */ diff --git a/sys/arm64/include/armreg.h b/sys/arm64/include/armreg.h index aca3d4c07450..aa9b672ad85a 100644 --- a/sys/arm64/include/armreg.h +++ b/sys/arm64/include/armreg.h @@ -34,25 +34,9 @@ #ifndef _MACHINE_ARMREG_H_ #define _MACHINE_ARMREG_H_ -#define INSN_SIZE 4 - -#define __MRS_REG_ALT_NAME(op0, op1, crn, crm, op2) \ - S##op0##_##op1##_C##crn##_C##crm##_##op2 -#define _MRS_REG_ALT_NAME(op0, op1, crn, crm, op2) \ - __MRS_REG_ALT_NAME(op0, op1, crn, crm, op2) -#define MRS_REG_ALT_NAME(reg) \ - _MRS_REG_ALT_NAME(reg##_op0, reg##_op1, reg##_CRn, reg##_CRm, reg##_op2) - +#include -#define READ_SPECIALREG(reg) \ -({ uint64_t _val; \ - __asm __volatile("mrs %0, " __STRING(reg) : "=&r" (_val)); \ - _val; \ -}) -#define WRITE_SPECIALREG(reg, _val) \ - __asm __volatile("msr " __STRING(reg) ", %0" : : "r"((uint64_t)_val)) - -#define UL(x) UINT64_C(x) +#define INSN_SIZE 4 /* AFSR0_EL1 - Auxiliary Fault Status Register 0 */ #define AFSR0_EL1_REG MRS_REG_ALT_NAME(AFSR0_EL1) diff --git a/sys/arm64/include/hypervisor.h b/sys/arm64/include/hypervisor.h index 8feabd2b981b..7d405e63cd8d 100644 --- a/sys/arm64/include/hypervisor.h +++ b/sys/arm64/include/hypervisor.h @@ -30,6 +30,8 @@ #ifndef _MACHINE_HYPERVISOR_H_ #define _MACHINE_HYPERVISOR_H_ +#include + /* * These registers are only useful when in hypervisor context, * e.g. specific to EL2, or controlling the hypervisor.