From owner-freebsd-smp Fri Nov 5 10:23:52 1999 Delivered-To: freebsd-smp@freebsd.org Received: from palrel3.hp.com (palrel3.hp.com [156.153.255.226]) by hub.freebsd.org (Postfix) with ESMTP id B0D251522A for ; Fri, 5 Nov 1999 10:23:44 -0800 (PST) (envelope-from darrylo@sr.hp.com) Received: from postal.sr.hp.com (root@postal.sr.hp.com [15.4.46.173]) by palrel3.hp.com (8.8.6 (PHNE_17135)/8.8.5tis) with ESMTP id KAA18386; Fri, 5 Nov 1999 10:22:18 -0800 (PST) Received: from mina.sr.hp.com (root@mina.sr.hp.com [15.4.42.247]) by postal.sr.hp.com with ESMTP (8.8.6 (PHNE_17190)/8.7.3 TIS 5.0) id KAA14230; Fri, 5 Nov 1999 10:22:21 -0800 (PST) Received: from localhost (darrylo@mina.sr.hp.com [15.4.42.247]) by mina.sr.hp.com with ESMTP (8.8.6 (PHNE_17135)/8.7.3 TIS 5.0) id KAA25575; Fri, 5 Nov 1999 10:22:09 -0800 (PST) Message-Id: <199911051822.KAA25575@mina.sr.hp.com> To: "Eric J. Schwertfeger" Cc: Adam Strohl , "Daniel O'Connor" , freebsd-smp@FreeBSD.ORG Subject: Re: Dual Celeron + FreeBSD? Reply-To: Darryl Okahata In-reply-to: Your message of "Fri, 05 Nov 1999 08:45:04 PST." Mime-Version: 1.0 (generated by tm-edit 7.108) Content-Type: text/plain; charset=US-ASCII Date: Fri, 05 Nov 1999 10:22:08 -0800 From: Darryl Okahata Sender: owner-freebsd-smp@FreeBSD.ORG Precedence: bulk X-Loop: FreeBSD.org "Eric J. Schwertfeger" wrote: > I agree for the most part, on single-processor machines, though it's > actually a quarter the cache. The reduced, faster cache causes a single > celeron to be more memory-bandwidth sensitive. An SMP machine, however, > has two CPUs contending for the same bandwidth, and for some processes, > that can be fatal. I'd like to emphasize Eric's point. With SMP, memory bandwidth and contention are very important: * A non-overclocked Celeron has a FSB of 66MHz. P2s (350MHz+) and above have a 100MHz FSB. * Celerons have only 128K L2 cache, although it is zero-wait state. With SMP, you can have processes that cause lots of memory contention (e.g., simple calls like "bzero()", "memcpy()", etc, can blow away the cache contents, and force the CPU to go directly to main memory). A larger cache helps to prevent memory contention between CPUs (although the non-zero-wait-state nature makes it less useful). > I've done make buildworld's on both my dual Celeron and my dual PPro (the > ones with 512K cache). The difference between single and dual celeron is > minimal, about 10%. On the dual PPro machine, the speed improvement, > using the same disk subsystem, was 80%. Yes, on processes that aren't > memory intensive, dual Celerons rock. In fact, on most things, I see > closer to 40-50% improvement with dual Celerons, the make buildworld is > rather memory intensive. The numbers I've seen thrown around (and I haven't verified them) are: 2 Celerons -> ~1.5X a single CPU 2 P2s (350MHz+) -> ~1.8X a single CPU This is, of course, simplistic. -- Darryl Okahata darrylo@sr.hp.com DISCLAIMER: this message is the author's personal opinion and does not constitute the support, opinion, or policy of Agilent Technologies, or of the little green men that have been following him all day. To Unsubscribe: send mail to majordomo@FreeBSD.org with "unsubscribe freebsd-smp" in the body of the message