From owner-freebsd-arm@freebsd.org Sun Dec 30 17:58:54 2018 Return-Path: Delivered-To: freebsd-arm@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 89382142FCEB for ; Sun, 30 Dec 2018 17:58:54 +0000 (UTC) (envelope-from ian@freebsd.org) Received: from outbound2m.ore.mailhop.org (outbound2m.ore.mailhop.org [54.149.155.156]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 98AB08EA02 for ; Sun, 30 Dec 2018 17:58:53 +0000 (UTC) (envelope-from ian@freebsd.org) ARC-Seal: i=1; a=rsa-sha256; t=1546191728; cv=none; d=outbound.mailhop.org; s=arc-outbound20181012; b=BnnkzFOnK1f2s4qrnBSytJfcyH5RvWo76wFeya/1B4PMPzHeICGk/mDTWUVkcK84eQfXFEUyC11gD VdIMPA8Zv2WiCfb/0HHNt0rEfGQg42FmQr9rIf8m2HHQxP6uoI2sFo161puIpMdjfUZzlOBlkfxaqF iOu/0A1M3wK7lyUdVKNRzpJ8T7HvtrraUnpxFyrD9oKfV7OPtWvBFZHLt77R9jwgACtJ7rr/ZByOWG XHV5Xm/bqyJhnkWAzwQjm0gM6EB31GfCjGPsy2IJ2YI8FUphlP4JZK9hXhEiw0R0ZaclkBTEOacm08 X68a+3TJPrArhOq42Ae8IiFbxFA6f1w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=outbound.mailhop.org; s=arc-outbound20181012; h=content-transfer-encoding:mime-version:content-type:references:in-reply-to: date:to:from:subject:message-id:dkim-signature:from; bh=8L2y8opAe0zkyLZxIIBYC5ChyqQUSVcRKBXdRMGmf24=; b=jb4YxYzAyVmGkOs9a9yvEpnnyUjv0z22Qx1WSmjjajUjgfYFM0qJs/JGk64oQEc3GXIhxiI6hFcEi +B+gqU9B0LmFzujVanupVgEADnCUtm5KrFJFoXpE38PFbc8iGGsu2+PtLHr02nTVpq5mJqURKKXLn+ 1biCEUhl5Lx9qdmtsptmdmL87kqbjQTgmmQ3jPfetYZwqRmKkCVkeo4JlZfXu5CY4yxIcYqVxTUOkZ LnB4jNKr8/WvOlPJc/hQyhX/QmLwZHzocrEpViWtze1NWGsnizYYmoVRyJ/dK280WkbskDH50Fanje 3pQgWMRU1t9ElI/joDlMJdyQo8xHBfA== ARC-Authentication-Results: i=1; outbound4.ore.mailhop.org; spf=softfail smtp.mailfrom=freebsd.org smtp.remote-ip=67.177.211.60; dmarc=none header.from=freebsd.org; arc=none header.oldest-pass=0; DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=outbound.mailhop.org; s=dkim-high; h=content-transfer-encoding:mime-version:content-type:references:in-reply-to: date:to:from:subject:message-id:from; bh=8L2y8opAe0zkyLZxIIBYC5ChyqQUSVcRKBXdRMGmf24=; b=IkZTcIg5uqQR6VvUhNjlaQlVtmY/Mro5/vh2ekMGsE5DB8F0qpjH+AhbkFa9gGZb10BUE8SALk+eH YyD7O4WItZdaSWSwxqmr7/Ic9wStTY/bKKpKps97eyHwcWFcXYas4o7ebdLPXvPvJFBy8yWzrZgQ5x KUj5ZJmSzY+cOV8btinqBCNSfW3xlQDf7dfqe27pEFanbggQajSAhjNlye4fWCWtZV69J5ot0Y3ycu UPlV2rgpQC7udqt7uz7cUY0hpgQntmqdI/NyijMbFyC3Sxje8pJsPTRHBFVkc+VpTZZCpnrCcqIq+4 dPQk5RSzQBcP2MI9hCYmAC3Pq7LWaqg== X-MHO-RoutePath: aGlwcGll X-MHO-User: 396267ac-0c5a-11e9-befd-af03bedce89f X-Report-Abuse-To: https://support.duocircle.com/support/solutions/articles/5000540958-duocircle-standard-smtp-abuse-information X-Originating-IP: 67.177.211.60 X-Mail-Handler: DuoCircle Outbound SMTP Received: from ilsoft.org (unknown [67.177.211.60]) by outbound4.ore.mailhop.org (Halon) with ESMTPSA id 396267ac-0c5a-11e9-befd-af03bedce89f; Sun, 30 Dec 2018 17:42:07 +0000 (UTC) Received: from rev (rev [172.22.42.240]) by ilsoft.org (8.15.2/8.15.2) with ESMTP id wBUHgd5B028987; Sun, 30 Dec 2018 10:42:39 -0700 (MST) (envelope-from ian@freebsd.org) Message-ID: <1546191759.78877.91.camel@freebsd.org> Subject: Re: SPI start bit (9 bit) for BBB From: Ian Lepore To: SAITOU Toshihide , freebsd-arm@freebsd.org Date: Sun, 30 Dec 2018 10:42:39 -0700 In-Reply-To: <20181231.003356.1147810385398844555.toshi@ruby.ocn.ne.jp> References: <20181231.003356.1147810385398844555.toshi@ruby.ocn.ne.jp> Content-Type: text/plain; charset="ISO-8859-1" X-Mailer: Evolution 3.18.5.1 FreeBSD GNOME Team Port Mime-Version: 1.0 Content-Transfer-Encoding: 8bit X-Rspamd-Queue-Id: 98AB08EA02 X-Spamd-Bar: -- Authentication-Results: mx1.freebsd.org X-Spamd-Result: default: False [-2.99 / 15.00]; local_wl_from(0.00)[freebsd.org]; NEURAL_HAM_MEDIUM(-1.00)[-1.000,0]; NEURAL_HAM_SHORT(-0.99)[-0.988,0]; ASN(0.00)[asn:16509, ipnet:54.148.0.0/15, country:US]; NEURAL_HAM_LONG(-1.00)[-1.000,0] X-BeenThere: freebsd-arm@freebsd.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: "Porting FreeBSD to ARM processors." List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 30 Dec 2018 17:58:54 -0000 On Mon, 2018-12-31 at 00:33 +0900, SAITOU Toshihide wrote: > In 3-line serial protcol, there is a type using additional 1-bit to > specify command or data.  The BBB can handle this, so I can use with > the following patch (unskillful and maybe side effects exist).  I > hope this will attract someones interest to implement this and also > SPI frequency and mode. > > > --- arm/ti/ti_spi.c.orig 2018-12-22 00:47:12.096034000 +0900 > +++ arm/ti/ti_spi.c 2018-12-30 23:58:00.000000000 +0900 > @@ -493,6 +493,7 @@ ti_spi_transfer(device_t dev, device_t child, > struct s >   /* Disable the FIFO. */ >   TI_SPI_WRITE(sc, MCSPI_XFERLEVEL, 0); >   > +#if 0 >   /* 8 bits word, d0 miso, d1 mosi, mode 0 and CS active low. > */ >   reg = TI_SPI_READ(sc, MCSPI_CONF_CH(sc->sc_cs)); >   reg &= ~(MCSPI_CONF_FFER | MCSPI_CONF_FFEW | > MCSPI_CONF_SBPOL | > @@ -501,6 +502,7 @@ ti_spi_transfer(device_t dev, device_t child, > struct s >       MCSPI_CONF_DMAW | MCSPI_CONF_EPOL); >   reg |= MCSPI_CONF_DPE0 | MCSPI_CONF_EPOL | > MCSPI_CONF_WL8BITS; >   TI_SPI_WRITE(sc, MCSPI_CONF_CH(sc->sc_cs), reg); > +#endif >   >  #if 0 >   /* Enable channel interrupts. */ > @@ -558,6 +560,70 @@ ti_spi_get_node(device_t bus, device_t dev) >   return (ofw_bus_get_node(bus)); >  } >   > +static int > +ti_spi_sbe(device_t dev, device_t child, uint32_t *request) > +{ > + struct ti_spi_softc *sc; > + uint32_t reg; > + > + sc = device_get_softc(dev); > + > + TI_SPI_LOCK(sc); > + > + /* If the controller is in use wait until it is available. > */ > + while (sc->sc_flags & TI_SPI_BUSY) > + mtx_sleep(dev, &sc->sc_mtx, 0, "ti_spi", 0); > + > + /* Now we have control over SPI controller. */ > + sc->sc_flags = TI_SPI_BUSY; > + > + reg = TI_SPI_READ(sc, MCSPI_CONF_CH(sc->sc_cs)); > + if (*request) > + reg |= MCSPI_CONF_SBE; > + else > + reg &= ~MCSPI_CONF_SBE; > + TI_SPI_WRITE(sc, MCSPI_CONF_CH(sc->sc_cs), reg); > + > + /* Release the controller and wakeup the next thread waiting > for it. */ > + sc->sc_flags = 0; > + wakeup_one(dev); > + TI_SPI_UNLOCK(sc); > + > + return (0); > +} > + > +static int > +ti_spi_sbpol(device_t dev, device_t child, uint32_t *request) > +{ > + struct ti_spi_softc *sc; > + uint32_t reg; > + > + sc = device_get_softc(dev); > + > + TI_SPI_LOCK(sc); > + > + /* If the controller is in use wait until it is available. > */ > + while (sc->sc_flags & TI_SPI_BUSY) > + mtx_sleep(dev, &sc->sc_mtx, 0, "ti_spi", 0); > + > + /* Now we have control over SPI controller. */ > + sc->sc_flags = TI_SPI_BUSY; > + > + reg = TI_SPI_READ(sc, MCSPI_CONF_CH(sc->sc_cs)); > + if (*request) > + reg |= MCSPI_CONF_SBPOL; > + else > + reg &= ~MCSPI_CONF_SBPOL; > + TI_SPI_WRITE(sc, MCSPI_CONF_CH(sc->sc_cs), reg); > + > + /* Release the controller and wakeup the next thread waiting > for it. */ > + sc->sc_flags = 0; > + wakeup_one(dev); > + TI_SPI_UNLOCK(sc); > + > + return (0); > +} > + >  static device_method_t ti_spi_methods[] = { >   /* Device interface */ >   DEVMETHOD(device_probe, ti_spi_probe), > @@ -569,6 +635,10 @@ static device_method_t ti_spi_methods[] = { >   >   /* ofw_bus interface */ >   DEVMETHOD(ofw_bus_get_node, ti_spi_get_node), > + > + /* provisional chip register interface for SBE and SBPOL */ > + DEVMETHOD(spibus_sbe, ti_spi_sbe), > + DEVMETHOD(spibus_sbpol, ti_spi_sbpol), >   >   DEVMETHOD_END >  }; > --- dev/spibus/spibus.c.orig 2018-12-29 23:50:40.262296000 > +0900 > +++ dev/spibus/spibus.c 2018-12-30 23:58:00.000000000 +0900 > @@ -226,6 +226,18 @@ spibus_transfer_impl(device_t dev, device_t > child, str >   return (SPIBUS_TRANSFER(device_get_parent(dev), child, > cmd)); >  } >   > +static int > +spibus_sbe_impl(device_t dev, device_t child, uint32_t *request) > +{ > + return (SPIBUS_SBE(device_get_parent(dev), child, request)); > +} > + > +static int > +spibus_sbpol_impl(device_t dev, device_t child, uint32_t *request) > +{ > + return (SPIBUS_SBPOL(device_get_parent(dev), child, > request)); > +} > + >  static device_method_t spibus_methods[] = { >   /* Device interface */ >   DEVMETHOD(device_probe, spibus_probe), > @@ -247,6 +259,9 @@ static device_method_t spibus_methods[] = { >   >   /* spibus interface */ >   DEVMETHOD(spibus_transfer, spibus_transfer_impl), > + > + DEVMETHOD(spibus_sbe, spibus_sbe_impl), > + DEVMETHOD(spibus_sbpol, spibus_sbpol_impl), >   >   DEVMETHOD_END >  }; > --- dev/spibus/spibus_if.m.orig 2018-12-22 00:49:22.440211000 > +0900 > +++ dev/spibus/spibus_if.m 2018-12-30 23:58:00.000000000 +0900 > @@ -39,3 +39,15 @@ METHOD int transfer { >   device_t child; >   struct spi_command *cmd; >  }; > + > +METHOD int sbe { > + device_t dev; > + device_t child; > + uint32_t *request; > +}; > + > +METHOD int sbpol { > + device_t dev; > + device_t child; > + uint32_t *request; > +}; > --- dev/spibus/spigen.c.orig 2018-12-29 20:19:20.584696000 > +0900 > +++ dev/spibus/spigen.c 2018-12-30 23:58:00.000000000 +0900 > @@ -248,6 +248,28 @@ spigen_transfer_mmapped(struct cdev *cdev, > struct spig >  } >   >  static int > +spigen_sbe(struct cdev *cdev, uint32_t *request) > +{ > + device_t dev = cdev->si_drv1; > + int error = 0; > + > + error = SPIBUS_SBE(device_get_parent(dev), dev, (uint32_t > *)request); > + > + return (error); > +} > + > +static int > +spigen_sbpol(struct cdev *cdev, uint32_t *request) > +{ > + device_t dev = cdev->si_drv1; > + int error = 0; > + > + error = SPIBUS_SBPOL(device_get_parent(dev), dev, (uint32_t > *)request); > + > + return (error); > +} > + > +static int >  spigen_ioctl(struct cdev *cdev, u_long cmd, caddr_t data, int fflag, >      struct thread *td) >  { > @@ -272,6 +294,12 @@ spigen_ioctl(struct cdev *cdev, u_long cmd, > caddr_t da >   break; >   case SPIGENIOC_SET_SPI_MODE: >   error = spibus_set_mode(dev, *(uint32_t *)data); > + break; > + case SPIGENIOC_SBE: > + error = spigen_sbe(cdev, (uint32_t *)data); > + break; > + case SPIGENIOC_SBPOL: > + error = spigen_sbpol(cdev, (uint32_t *)data); >   break; >   default: >   error = ENOTTY; > --- sys/spigenio.h.orig 2018-12-22 00:48:50.752200000 +0900 > +++ sys/spigenio.h 2018-12-30 23:58:00.000000000 +0900 > @@ -52,5 +52,7 @@ struct spigen_transfer_mmapped { >  #define SPIGENIOC_SET_CLOCK_SPEED  _IOW(SPIGENIOC_BASE, 3, uint32_t) >  #define SPIGENIOC_GET_SPI_MODE     _IOR(SPIGENIOC_BASE, 4, uint32_t) >  #define SPIGENIOC_SET_SPI_MODE     _IOW(SPIGENIOC_BASE, 5, uint32_t) > +#define SPIGENIOC_SBE              _IOW(SPIGENIOC_BASE, 6, uint32_t) > +#define SPIGENIOC_SBPOL            _IOW(SPIGENIOC_BASE, 7, uint32_t) >   >  #endif /* !_SYS_SPIGENIO_H_ */ > > -- I've been working with SPI devices for years, and I don't think I've ever heard of this SBE and SBPOL stuff. Can you point me to a standards document or something else that describes it? -- Ian