From owner-p4-projects@FreeBSD.ORG Sun May 8 07:19:42 2005 Return-Path: Delivered-To: p4-projects@freebsd.org Received: by hub.freebsd.org (Postfix, from userid 32767) id 1DE5116A4E3; Sun, 8 May 2005 07:19:42 +0000 (GMT) Delivered-To: perforce@freebsd.org Received: from mx1.FreeBSD.org (mx1.freebsd.org [216.136.204.125]) by hub.freebsd.org (Postfix) with ESMTP id E8E4B16A4E1 for ; Sun, 8 May 2005 07:19:41 +0000 (GMT) Received: from repoman.freebsd.org (repoman.freebsd.org [216.136.204.115]) by mx1.FreeBSD.org (Postfix) with ESMTP id C0E9E43D6D for ; Sun, 8 May 2005 07:19:41 +0000 (GMT) (envelope-from marcel@freebsd.org) Received: from repoman.freebsd.org (localhost [127.0.0.1]) by repoman.freebsd.org (8.13.1/8.13.1) with ESMTP id j487JfLp038672 for ; Sun, 8 May 2005 07:19:41 GMT (envelope-from marcel@freebsd.org) Received: (from perforce@localhost) by repoman.freebsd.org (8.13.1/8.13.1/Submit) id j487Jfq1038669 for perforce@freebsd.org; Sun, 8 May 2005 07:19:41 GMT (envelope-from marcel@freebsd.org) Date: Sun, 8 May 2005 07:19:41 GMT Message-Id: <200505080719.j487Jfq1038669@repoman.freebsd.org> X-Authentication-Warning: repoman.freebsd.org: perforce set sender to marcel@freebsd.org using -f From: Marcel Moolenaar To: Perforce Change Reviews Subject: PERFORCE change 76675 for review X-BeenThere: p4-projects@freebsd.org X-Mailman-Version: 2.1.1 Precedence: list List-Id: p4 projects tree changes List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 08 May 2005 07:19:43 -0000 http://perforce.freebsd.org/chv.cgi?CH=76675 Change 76675 by marcel@marcel_nfs on 2005/05/08 07:19:29 Initialization step 2a+4: Reprogram the general registers, CRTC and sequencer. Reenable the sync signals. To do: reprogram the graphics controller, attribute controller and clear the frame buffer. Tested on: i386 Affected files ... .. //depot/projects/tty/sys/dev/vga/vga.c#6 edit Differences ... ==== //depot/projects/tty/sys/dev/vga/vga.c#6 (text+ko) ==== @@ -42,6 +42,10 @@ bus_space_read_1(sc->vga_crtc.bst, sc->vga_crtc.bsh, reg) #define CRTC_WRITE(sc, reg, val) \ bus_space_write_1(sc->vga_crtc.bst, sc->vga_crtc.bsh, reg, val) +#define REG_READ(sc, reg) \ + bus_space_read_1(sc->vga_reg.bst, sc->vga_reg.bsh, reg) +#define REG_WRITE(sc, reg, val) \ + bus_space_write_1(sc->vga_reg.bst, sc->vga_reg.bsh, reg, val) struct vga_softc vga_console; devclass_t vga_devclass; @@ -71,7 +75,90 @@ x = CRTC_READ(sc, VGA_CRTC_DATA); CRTC_WRITE(sc, VGA_CRTC_DATA, x & ~VGA_CRTC_MC_HR); - /* TODO -- set the VGA adapter in 640x480x16 mode */ + /* Unprotect CRTC registers 0-7. */ + CRTC_WRITE(sc, VGA_CRTC_ADDRESS, VGA_CRTC_VERT_RETRACE_END); + x = CRTC_READ(sc, VGA_CRTC_DATA); + CRTC_WRITE(sc, VGA_CRTC_DATA, x & ~VGA_CRTC_VRE_PR); + + /* + * Set the VGA adapter in mode 0x12 (640x480x16). + */ + /* Reprogram the CRTC. */ + CRTC_WRITE(sc, VGA_CRTC_ADDRESS, VGA_CRTC_HORIZ_TOTAL); + CRTC_WRITE(sc, VGA_CRTC_DATA, 0x5f); /* 760 */ + CRTC_WRITE(sc, VGA_CRTC_ADDRESS, VGA_CRTC_HORIZ_DISP_END); + CRTC_WRITE(sc, VGA_CRTC_DATA, 0x4f); /* 640 - 8 */ + CRTC_WRITE(sc, VGA_CRTC_ADDRESS, VGA_CRTC_START_HORIZ_BLANK); + CRTC_WRITE(sc, VGA_CRTC_DATA, 0x50); /* 640 */ + CRTC_WRITE(sc, VGA_CRTC_ADDRESS, VGA_CRTC_END_HORIZ_BLANK); + CRTC_WRITE(sc, VGA_CRTC_DATA, VGA_CRTC_EHB_CR + 2); + CRTC_WRITE(sc, VGA_CRTC_ADDRESS, VGA_CRTC_START_HORIZ_RETRACE); + CRTC_WRITE(sc, VGA_CRTC_DATA, 0x54); /* 672 */ + CRTC_WRITE(sc, VGA_CRTC_ADDRESS, VGA_CRTC_END_HORIZ_RETRACE); + CRTC_WRITE(sc, VGA_CRTC_DATA, VGA_CRTC_EHR_EHB + 0); + CRTC_WRITE(sc, VGA_CRTC_ADDRESS, VGA_CRTC_VERT_TOTAL); + CRTC_WRITE(sc, VGA_CRTC_DATA, 0x0b); /* 523 */ + CRTC_WRITE(sc, VGA_CRTC_ADDRESS, VGA_CRTC_OVERFLOW); + CRTC_WRITE(sc, VGA_CRTC_DATA, VGA_CRTC_OF_VT9 | VGA_CRTC_OF_LC8 | + VGA_CRTC_OF_VBS8 | VGA_CRTC_OF_VRS8 | VGA_CRTC_OF_VDE8); + CRTC_WRITE(sc, VGA_CRTC_ADDRESS, VGA_CRTC_PRESET_ROW_SCAN); + CRTC_WRITE(sc, VGA_CRTC_DATA, 0); + CRTC_WRITE(sc, VGA_CRTC_ADDRESS, VGA_CRTC_MAX_SCAN_LINE); + CRTC_WRITE(sc, VGA_CRTC_DATA, VGA_CRTC_MSL_LC9); + CRTC_WRITE(sc, VGA_CRTC_ADDRESS, VGA_CRTC_CURSOR_START); + CRTC_WRITE(sc, VGA_CRTC_DATA, 0); + CRTC_WRITE(sc, VGA_CRTC_ADDRESS, VGA_CRTC_CURSOR_END); + CRTC_WRITE(sc, VGA_CRTC_DATA, 0); + CRTC_WRITE(sc, VGA_CRTC_ADDRESS, VGA_CRTC_START_ADDR_HIGH); + CRTC_WRITE(sc, VGA_CRTC_DATA, 0); + CRTC_WRITE(sc, VGA_CRTC_ADDRESS, VGA_CRTC_START_ADDR_LOW); + CRTC_WRITE(sc, VGA_CRTC_DATA, 0); + CRTC_WRITE(sc, VGA_CRTC_ADDRESS, VGA_CRTC_CURSOR_LOC_HIGH); + CRTC_WRITE(sc, VGA_CRTC_DATA, 0); + CRTC_WRITE(sc, VGA_CRTC_ADDRESS, VGA_CRTC_CURSOR_LOC_LOW); + CRTC_WRITE(sc, VGA_CRTC_DATA, 0x59); + CRTC_WRITE(sc, VGA_CRTC_ADDRESS, VGA_CRTC_VERT_RETRACE_START); + CRTC_WRITE(sc, VGA_CRTC_DATA, 0xea); /* 480 + 10 */ + CRTC_WRITE(sc, VGA_CRTC_ADDRESS, VGA_CRTC_VERT_RETRACE_END); + CRTC_WRITE(sc, VGA_CRTC_DATA, 0x8c); + CRTC_WRITE(sc, VGA_CRTC_ADDRESS, VGA_CRTC_VERT_DISPLAY_END); + CRTC_WRITE(sc, VGA_CRTC_DATA, 0xdf); /* 480 - 1*/ + CRTC_WRITE(sc, VGA_CRTC_ADDRESS, VGA_CRTC_OFFSET); + CRTC_WRITE(sc, VGA_CRTC_DATA, 0x28); + CRTC_WRITE(sc, VGA_CRTC_ADDRESS, VGA_CRTC_UNDERLINE_LOC); + CRTC_WRITE(sc, VGA_CRTC_DATA, 0); + CRTC_WRITE(sc, VGA_CRTC_ADDRESS, VGA_CRTC_START_VERT_BLANK); + CRTC_WRITE(sc, VGA_CRTC_DATA, 0xe7); /* 480 + 7 */ + CRTC_WRITE(sc, VGA_CRTC_ADDRESS, VGA_CRTC_END_VERT_BLANK); + CRTC_WRITE(sc, VGA_CRTC_DATA, 0x04); + CRTC_WRITE(sc, VGA_CRTC_ADDRESS, VGA_CRTC_MODE_CONTROL); + CRTC_WRITE(sc, VGA_CRTC_DATA, VGA_CRTC_MC_WB | VGA_CRTC_MC_AW | + VGA_CRTC_MC_SRS | VGA_CRTC_MC_CMS); + CRTC_WRITE(sc, VGA_CRTC_ADDRESS, VGA_CRTC_LINE_COMPARE); + CRTC_WRITE(sc, VGA_CRTC_DATA, 0xff); /* 480 + 31 */ + /* Reprogram the general registers. */ + REG_WRITE(sc, VGA_GEN_MISC_OUTPUT_W, VGA_GEN_MO_VSP | VGA_GEN_MO_HSP | + VGA_GEN_MO_PB | VGA_GEN_MO_ER | VGA_GEN_MO_IOA); + REG_WRITE(sc, VGA_EXT_FEATURE_CTRL, 0); + /* Reprogram the sequencer. */ + REG_WRITE(sc, VGA_SEQ_ADDRESS, VGA_SEQ_RESET); + REG_WRITE(sc, VGA_SEQ_DATA, VGA_SEQ_RST_SR | VGA_SEQ_RST_NAR); + REG_WRITE(sc, VGA_SEQ_ADDRESS, VGA_SEQ_CLOCKING_MODE); + REG_WRITE(sc, VGA_SEQ_DATA, VGA_SEQ_CM_89); + REG_WRITE(sc, VGA_SEQ_ADDRESS, VGA_SEQ_MAP_MASK); + REG_WRITE(sc, VGA_SEQ_DATA, VGA_SEQ_MM_EM3 | VGA_SEQ_MM_EM2 | + VGA_SEQ_MM_EM1 | VGA_SEQ_MM_EM0); + REG_WRITE(sc, VGA_SEQ_ADDRESS, VGA_SEQ_CHAR_MAP_SELECT); + REG_WRITE(sc, VGA_SEQ_DATA, 0x0); + REG_WRITE(sc, VGA_SEQ_ADDRESS, VGA_SEQ_MEMORY_MODE); + REG_WRITE(sc, VGA_SEQ_DATA, VGA_SEQ_MM_OE | VGA_SEQ_MM_EM); + /* Reprogram the attribute controller. */ + /* Reprogram the graphics controller. */ + + /* Enable the sync signals. */ + CRTC_WRITE(sc, VGA_CRTC_ADDRESS, VGA_CRTC_MODE_CONTROL); + x = CRTC_READ(sc, VGA_CRTC_DATA); + CRTC_WRITE(sc, VGA_CRTC_DATA, x | VGA_CRTC_MC_HR); sc->vga_enable = 1; return (0);