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[88.208.79.100]) by smtp.gmail.com with ESMTPSA id u4sm19424866wrq.22.2019.11.12.06.29.08 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 12 Nov 2019 06:29:08 -0800 (PST) Sender: Michal Meloun From: Michal Meloun X-Google-Original-From: Michal Meloun Reply-To: mmel@freebsd.org Subject: Re: Rock64 clock errors following r354558 To: Peter Jeremy Cc: freebsd-arm@freebsd.org References: <20191112085019.GC50716@server.rulingia.com> Autocrypt: addr=mmel@freebsd.org; prefer-encrypt=mutual; keydata= xsBNBFYuVRkBCADZiwLCCne3wG9b9k+R2Neo5zVo2bLaZRfNNY/v9kg283i0sb1Da4EdEiNT 15El5UyozhphUIbIR/zrVpxF1TvvFdoCyzx6a68bNY2d9dBrDcNDZC+XnyDdHQoobN87DWT1 mRVkmbg9LHZ/SVUOkGYuWyE+8UYeDAcUizuXwSK5zFWmeTyIoWNa68ifrWLfQe0p4x5jC/AI VURCi17p360vU4fhgwoMvEEhrRBWCr4DYHToFjIt2WdBy3GR1qoO0+Xkd6G+OoBULo+XDfgu L2WdPvh0K69F9/LgHkMmG5Il7SCe62QGpG2vaCgRV7BQhLX+kxlvM+WrdRatWRml4Y/3ABEB AAHNIE1pY2hhbCBNZWxvdW4gPG1tZWxAZnJlZWJzZC5vcmc+wsCuBBMBCgBBAhsDBQsJCAcD BRUKCQgLBRYDAgEAAh4BAheAAhkBFiEEAN1KEEuAn+Apg413aR6ya17FqqoFAlw3aO8FCQ9v FVYAIQkQaR6ya17FqqoWIQQA3UoQS4Cf4CmDjXdpHrJrXsWqqsgXB/9X81G4C63DVxn8dELB +nTQpj7yDvfQrA5oAyE9i+ry2p/ySsPCEVFa32zgNJVNUlQLZ1FlrmDUxLvuJAv9ZbMFSEmP utbi4ylwqmLtReLTrSwqucT7VkG9qcbxgIxMcrFCBAMPRwGqzI4B+tID4/LJrf8fICHW++NB l+7m9bEDVfk1fmXkq2iemsn7JtVpzA5bfjJ9ZJf6dzHTz0mlSSd6cZ0j6BWgp9rq6H/xiIJl MjmmjEG22s4Hw0Z/KVOxNNNvDamSKt5WRzzuqr74j1sE21OpY5mMH/coFR3irW94RRrgxLrd Na0C9wRyzEeIG/gAfqek87+I/Jy4YaGqV1PUzsBNBFYuVRkBCAC6oEZH0ttQ/zqlhPZl34dm yI66fbgvE9DAropm7KwHSyjTaKxrtpxPq3m4F/J+Z2DN++xzp2pTxsjrl7wm0PDBVUXVjh8X pyY1yYmpTXQbDn9sC72t70klbHaD84m1gyHCaoQTkNxLobCC8lkj72GChIsveZn4aw7bk0zg GFUfWjUAThDc7QdkwycjMf6mZrRq6BldzdB6nXv85xz7UDvERufxUBjHxzCORhTLsnK9XHh5 y6P6L66gJeE2FflB0hyfhQxPXbfcFx3JVm1mwtMjboHIWauq4aOSY37+Gtr+z6cp9x6A4p4d ZVj+4WANGTRMRh3pC511lajv5cxkumzBABEBAAHCwGUEGAEKAA8CGwwFAlmMEcMFCQcgI6oA CgkQaR6ya17Fqqq7Kwf+IOBEiuUy8VMYvKS1nCz8r8LTeBZn+1bAlXn5IWpGhqwz5n735xvj hcDetF6qJ4uxgXmpJdNccE+ESDX71X0oQ8unB6S0u0C/zPKc37pVV9/DJFZDg8hmYcIxPo8k /5GTQNTpWsNzdyHnx6t267JEOxuHfaD3qdgw28OwuEO+rjgY8ct+CVQdFjrAejcjEAfYeixp Y0LXRHXclKsJ0Wc8x4hr6dIT7XWEB0GZam4+BVfZU0Su2vBIGvsuzIJnjIs7Rs3l8ozT9Nq9 z0Rwj2oMGue2z8R9mgIeEO1MwQWdBkzJuwyyjbQj+fFg8W5a64Wfu5B6hivBbG3XlKQ3RGC1 XcLAkwQYAQoAJgIbDBYhBADdShBLgJ/gKYONd2kesmtexaqqBQJcN2mbBQkPbxYCACEJEGke smtexaqqFiEEAN1KEEuAn+Apg413aR6ya17FqqrTqwf/TpJP3Ztv5gLN7WwOpZSjmQMH1MAa J8Bu2ISvXTm+TaP2yaGPBvbNiFV6sFiqgg79aiguDPKTFzw/X1bHzTxvBgNRma6WaGcRxbXl 2R6BNYK6VsqRNE94adVtIUDVlyr9DErhDEVSlNZv4si2tdF+6vAWirRA7N+V3wwoe3lYNb6o irVshZ9bvsvRstWbXP0ik7PJkLzGDVHQWblerzdFUs9yOsA/R1X6OhKNzO3FaaqkPioa6xog gmED32cKRQCUkoFd20eTtAZTWhiiTqFU1dcnsUW1RErbMIhT/CRUKelPkt56hBRaG+3WkAS8 YvNKFFUZ+nhHc0fLQYSMu7G3gw== Message-ID: <5e508cb2-45ea-ecd8-b245-e9812dcda615@freebsd.org> Date: Tue, 12 Nov 2019 15:29:08 +0100 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: <20191112085019.GC50716@server.rulingia.com> Content-Type: text/plain; charset=windows-1252 Content-Language: en-US Content-Transfer-Encoding: 7bit X-Rspamd-Queue-Id: 47C99M5syMz4c9g X-Spamd-Bar: -- Authentication-Results: mx1.freebsd.org; dkim=pass header.d=gmail.com header.s=20161025 header.b=EVieJCkf; dmarc=pass (policy=none) header.from=gmail.com; spf=pass (mx1.freebsd.org: domain of melounmichal@gmail.com designates 2a00:1450:4864:20::32d as permitted sender) smtp.mailfrom=melounmichal@gmail.com X-Spamd-Result: default: False [-3.00 / 15.00]; RCVD_VIA_SMTP_AUTH(0.00)[]; HAS_REPLYTO(0.00)[mmel@freebsd.org]; TO_DN_SOME(0.00)[]; R_SPF_ALLOW(-0.20)[+ip6:2a00:1450:4000::/36:c]; FREEMAIL_FROM(0.00)[gmail.com]; RCVD_COUNT_THREE(0.00)[3]; DKIM_TRACE(0.00)[gmail.com:+]; RCPT_COUNT_TWO(0.00)[2]; DMARC_POLICY_ALLOW(-0.50)[gmail.com,none]; FROM_EQ_ENVFROM(0.00)[]; IP_SCORE(0.00)[ip: (-9.17), ipnet: 2a00:1450::/32(-2.74), asn: 15169(-2.00), country: US(-0.05)]; MIME_TRACE(0.00)[0:+]; FREEMAIL_ENVFROM(0.00)[gmail.com]; ASN(0.00)[asn:15169, ipnet:2a00:1450::/32, country:US]; TAGGED_FROM(0.00)[]; DWL_DNSWL_NONE(0.00)[gmail.com.dwl.dnswl.org : 127.0.5.0]; ARC_NA(0.00)[]; NEURAL_HAM_MEDIUM(-1.00)[-1.000,0]; R_DKIM_ALLOW(-0.20)[gmail.com:s=20161025]; FROM_HAS_DN(0.00)[]; NEURAL_HAM_LONG(-1.00)[-1.000,0]; MIME_GOOD(-0.10)[text/plain]; PREVIOUSLY_DELIVERED(0.00)[freebsd-arm@freebsd.org]; REPLYTO_DOM_NEQ_FROM_DOM(0.00)[]; IP_SCORE_FREEMAIL(0.00)[]; TO_MATCH_ENVRCPT_SOME(0.00)[]; RCVD_IN_DNSWL_NONE(0.00)[d.2.3.0.0.0.0.0.0.0.0.0.0.0.0.0.0.2.0.0.4.6.8.4.0.5.4.1.0.0.a.2.list.dnswl.org : 127.0.5.0]; RCVD_TLS_ALL(0.00)[] X-BeenThere: freebsd-arm@freebsd.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: "Porting FreeBSD to ARM processors." List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Nov 2019 14:29:12 -0000 On 12.11.2019 9:50, Peter Jeremy wrote: > Hi Michal, > > Somewhere between r354439 and r354592, my Rock64 (RK3328) has > started reporting errors setting the clocks on aclk_bus_pre and > aclk_peri_pre. My best guess is that it's somewhere in > r354554..r354558. I have had a quick look and noting jumps out at > me so I'm wondering if you have any ideas. > Hi Peter, i think that this can be caused by r354557. Can you, please, try it again with full debug log enabled? By changing '#if 0' to '#if 1' at line 71 in rk_clk_composite.c. Thanks, Michal > The relevant non-verbose messages are now: rk3328_cru0: RK3328 Clock and Reset Unit> mem 0xff440000-0xff440fff on ofwbus0 > rk3328_cru0: cannot get parent at idx 6 Cannot set frequency for > clk: aclk_bus_pre, error: 34 rk3328_cru0: Failed to set > aclk_bus_pre to a frequency of 15000000 Cannot set frequency for > clk: aclk_peri_pre, error: 34 rk3328_cru0: Failed to set > aclk_peri_pre to a frequency of 15000000 > > The "cannot get parent" has been around for as long as I can tell > but the "cannot set frequency" errors are both new. > > Looking back, my previous verbose boot was at r354239 and it > shows: rk3328_cru0: cannot get assigned clock at idx 5 rk3328_cru0: > cannot get parent at idx 6 rk3328_cru0: Set aclk_bus_pre to > 15000000 rk3328_cru0: Set aclk_peri_pre to 15000000 rk3328_cru0: > cannot get assigned clock at idx 8 > > With a verbose boot at r354607 (including some additional debug > printf's), it now shows: rk3328_cru0: cannot get assigned clock at > idx 5 rk3328_cru0: cannot get parent for aclk_bus_pre at idx 6 > rk_clk_composite_set_freq:(aclk_bus_pre)Finding best parent/div for > target freq of 15000000 > rk_clk_composite_set_freq:(aclk_bus_pre)Testing with parent cpll > (0) at freq 594000000 > rk_clk_composite_set_freq:(aclk_bus_pre)Testing with parent gpll > (1) at freq 576000000 rk_clk_composite_set_freq:(aclk_bus_pre)Best > divisor is 0 Cannot set frequency for clk: aclk_bus_pre, error: 34 > rk_clk_composite_recalc:(aclk_bus_pre)Read: muxdiv_offset=100, > val=2501 > rk_clk_composite_recalc:(aclk_bus_pre)parent_freq=576000000, div=6 > rk_clk_composite_recalc:(aclk_bus_pre)Final freq=96000000 > rk_clk_composite_recalc:(hclk_bus_pre)Read: muxdiv_offset=104, > val=1113 > rk_clk_composite_recalc:(hclk_bus_pre)parent_freq=96000000, div=2 > rk_clk_composite_recalc:(hclk_bus_pre)Final freq=48000000 > rk_clk_composite_recalc:(pclk_bus_pre)Read: muxdiv_offset=104, > val=1113 > rk_clk_composite_recalc:(pclk_bus_pre)parent_freq=96000000, div=2 > rk_clk_composite_recalc:(pclk_bus_pre)Final freq=48000000 > rk3328_cru0: Failed to set aclk_bus_pre to a frequency of 15000000 > rk_clk_composite_set_freq:(aclk_peri_pre)Finding best parent/div > for target freq of 15000000 > rk_clk_composite_set_freq:(aclk_peri_pre)Testing with parent cpll > (0) at freq 594000000 > rk_clk_composite_set_freq:(aclk_peri_pre)Testing with parent gpll > (1) at freq 576000000 rk_clk_composite_set_freq:(aclk_peri_pre)Best > divisor is 0 Cannot set frequency for clk: aclk_peri_pre, error: > 34 rk_clk_composite_recalc:(aclk_peri_pre)Read: muxdiv_offset=170, > val=4143 > rk_clk_composite_recalc:(aclk_peri_pre)parent_freq=576000000, > div=4 rk_clk_composite_recalc:(aclk_peri_pre)Final freq=144000000 > rk_clk_composite_recalc:(pclk_peri)Read: muxdiv_offset=0, val=40c8 > rk_clk_composite_recalc:(pclk_peri)parent_freq=144000000, div=1 > rk_clk_composite_recalc:(pclk_peri)Final freq=144000000 > rk_clk_composite_recalc:(hclk_peri)Read: muxdiv_offset=0, val=40c8 > rk_clk_composite_recalc:(hclk_peri)parent_freq=144000000, div=5 > rk_clk_composite_recalc:(hclk_peri)Final freq=28800000 rk3328_cru0: > Failed to set aclk_peri_pre to a frequency of 15000000 rk3328_cru0: > cannot get assigned clock at idx 8 >