From owner-svn-src-all@freebsd.org Thu Sep 7 21:33:29 2017 Return-Path: Delivered-To: svn-src-all@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 56F6AE11570; Thu, 7 Sep 2017 21:33:29 +0000 (UTC) (envelope-from cem@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 037AE777B2; Thu, 7 Sep 2017 21:33:28 +0000 (UTC) (envelope-from cem@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id v87LXSkS056239; Thu, 7 Sep 2017 21:33:28 GMT (envelope-from cem@FreeBSD.org) Received: (from cem@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id v87LXSLS056238; Thu, 7 Sep 2017 21:33:28 GMT (envelope-from cem@FreeBSD.org) Message-Id: <201709072133.v87LXSLS056238@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: cem set sender to cem@FreeBSD.org using -f From: Conrad Meyer Date: Thu, 7 Sep 2017 21:33:28 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r323289 - head/sys/x86/x86 X-SVN-Group: head X-SVN-Commit-Author: cem X-SVN-Commit-Paths: head/sys/x86/x86 X-SVN-Commit-Revision: 323289 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 07 Sep 2017 21:33:29 -0000 Author: cem Date: Thu Sep 7 21:33:27 2017 New Revision: 323289 URL: https://svnweb.freebsd.org/changeset/base/323289 Log: x86 MCA: Helpfully, print why ECC thresholding is not enabled on AMD Sponsored by: Dell EMC Isilon Modified: head/sys/x86/x86/mca.c Modified: head/sys/x86/x86/mca.c ============================================================================== --- head/sys/x86/x86/mca.c Thu Sep 7 21:31:07 2017 (r323288) +++ head/sys/x86/x86/mca.c Thu Sep 7 21:33:27 2017 (r323289) @@ -981,19 +981,25 @@ amd_thresholding_init(void) /* The counter must be valid and present. */ misc = rdmsr(MSR_MC_MISC(MC_AMDNB_BANK)); if ((misc & (MC_MISC_AMDNB_VAL | MC_MISC_AMDNB_CNTP)) != - (MC_MISC_AMDNB_VAL | MC_MISC_AMDNB_CNTP)) + (MC_MISC_AMDNB_VAL | MC_MISC_AMDNB_CNTP)) { + printf("%s: 0x%lx: !valid | !present\n", __func__, misc); return; + } /* The register should not be locked. */ - if ((misc & MC_MISC_AMDNB_LOCK) != 0) + if ((misc & MC_MISC_AMDNB_LOCK) != 0) { + printf("%s: 0x%lx: locked\n", __func__, misc); return; + } /* * If counter is enabled then either the firmware or another CPU * has already claimed it. */ - if ((misc & MC_MISC_AMDNB_CNTEN) != 0) + if ((misc & MC_MISC_AMDNB_CNTEN) != 0) { + printf("%s: 0x%lx: count already enabled\n", __func__, misc); return; + } /* * Configure an Extended Interrupt LVT register for reporting @@ -1001,10 +1007,15 @@ amd_thresholding_init(void) * extended register is available. */ amd_elvt = lapic_enable_mca_elvt(); - if (amd_elvt < 0) + if (amd_elvt < 0) { + printf("%s: lapic enable mca elvt failed: %d\n", __func__, amd_elvt); return; + } /* Re-use Intel CMC support infrastructure. */ + if (bootverbose) + printf("%s: Starting AMD thresholding\n", __func__); + cc = &amd_et_state[PCPU_GET(cpuid)]; cc->cur_threshold = 1; amd_thresholding_start(cc);