From owner-freebsd-current@FreeBSD.ORG Fri Nov 18 20:00:21 2005 Return-Path: X-Original-To: freebsd-current@freebsd.org Delivered-To: freebsd-current@freebsd.org Received: from mx1.FreeBSD.org (mx1.freebsd.org [216.136.204.125]) by hub.freebsd.org (Postfix) with ESMTP id A6E3616A41F for ; Fri, 18 Nov 2005 20:00:21 +0000 (GMT) (envelope-from dillon@apollo.backplane.com) Received: from apollo.backplane.com (apollo.backplane.com [216.240.41.2]) by mx1.FreeBSD.org (Postfix) with ESMTP id 5761343D45 for ; Fri, 18 Nov 2005 20:00:21 +0000 (GMT) (envelope-from dillon@apollo.backplane.com) Received: from apollo.backplane.com (localhost [127.0.0.1]) by apollo.backplane.com (8.13.4/8.13.4) with ESMTP id jAIJxvdh012618 for ; Fri, 18 Nov 2005 11:59:57 -0800 (PST) Received: (from dillon@localhost) by apollo.backplane.com (8.13.4/8.13.4/Submit) id jAIJxvYA012617; Fri, 18 Nov 2005 11:59:57 -0800 (PST) Date: Fri, 18 Nov 2005 11:59:57 -0800 (PST) From: Matthew Dillon Message-Id: <200511181959.jAIJxvYA012617@apollo.backplane.com> To: freebsd-current@freebsd.org References: <20051117010651.97608.qmail@web50303.mail.yahoo.com> <200511171702.20956.jhb@freebsd.org> <200511172330.jAHNUhgV007502@apollo.backplane.com> <200511181352.15149.jhb@freebsd.org> Subject: Re: Side note on Shuttle XPC / AMD X2 (SN95G5V3) (Re: [PATCH] nve(4) locking cleanup) X-BeenThere: freebsd-current@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Discussions about the use of FreeBSD-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 18 Nov 2005 20:00:21 -0000 :We've punted on using IRQ0 with lapic's altogether and use the lapic timer now :to drive hardclock, statclock, and profclock. Not only do some motherboards :not hook up IRQ0 to intpin 2 on the first I/O APIC requiring the use of mixed :mode to route IRQ0 on such boards, but on some recent systems such as the :Compaq R3000z amd64 laptops it seems that instead of pin 0 on the first I/O :APIC being an ExtINT pin, it is actually IRQ0 and there is no ExtINT pin (and :pin 2 on the first I/O APIC isn't hooked up to anything). I think IRQ0 with :APICs is only going to get worse and worse as time goes on. I'll probably be adding support for the LAPIC timer for APIC_IO builds after our next release. It hasn't been a priority because the current 8254 code, while crufty, is at least bug free. Since we do not have to access any hardware timers in the critical context switching path (I think FreeBSD still does that), access latency is not really an issue. 8254 interrupt routing is clearly becoming an issue so it will be a nice refreshing change to not have to deal with it. We have a SYSTIMER abstraction which is used for all high frequency one-shot and periodic events in the system. The SYSTIMER code is already 100% MPSAFE, cpu-localized, and designed to be able to use the LAPIC on each cpu, so it is really just a matter of actually wiring the LAPIC timers up to it. Since we can use the LAPIC with ICU (8259) interrupt routing we'll be able to use the LAPIC timer on all systems that have an LAPIC no matter the build. Most of DragonFly's periodic operations are no longer related to 'hz' in any way. So, e.g. the frequency for network polling, scheduling, statistics, profiling, interrupt rate limiting, emergency interrupt polling, etc, can all be set independantly of each other and some have even been wired into sysctl's so they can be changed on the fly. -Matt Matthew Dillon