From owner-freebsd-net@FreeBSD.ORG Tue Aug 26 20:42:35 2014 Return-Path: Delivered-To: freebsd-net@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [8.8.178.115]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTPS id 79DE9A38; Tue, 26 Aug 2014 20:42:35 +0000 (UTC) Received: from mail-lb0-x22d.google.com (mail-lb0-x22d.google.com [IPv6:2a00:1450:4010:c04::22d]) (using TLSv1 with cipher ECDHE-RSA-RC4-SHA (128/128 bits)) (Client CN "smtp.gmail.com", Issuer "Google Internet Authority G2" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id B2DD13B64; Tue, 26 Aug 2014 20:42:34 +0000 (UTC) Received: by mail-lb0-f173.google.com with SMTP id u10so2046691lbd.18 for ; Tue, 26 Aug 2014 13:42:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:date:message-id:subject:from:to:cc:content-type; bh=XQTPovTsDwy2L8+ESVO74mdFOiBQNio2qK9OAsZUc2c=; b=OLlJa4q1pTTMTrrwNju7aWzLjrRrg2s9K6DjnGYVGUwY8QyEeZEDGQKL9l42gUs8FI XYQFXxKJrqbj4sc/Ruh10dX16jgS9o1E0yEMUw+J5PP3rRCtB0C/5IYTfSZ05M2QlVPO eEPnUb5iqvsTXCe857CYMk9NimEKlNfWBTb2iWlRFQrYRqKoSXNpmiwssjhLYJ0c4lMk kapzj0GQpbRVULN+pvfU6Hn6kNSDd64AQY6CjOETSfE5gZGiiZ0Jt7vz+lQYqTjYt8MX /kvhm4dQBJlsraTeQxL83cnEsnHESpqt6D/XMCYYDxcDfQh5l1SssDfg92qTuF+KsFrT c4+A== MIME-Version: 1.0 X-Received: by 10.112.61.68 with SMTP id n4mr5141010lbr.91.1409085752709; Tue, 26 Aug 2014 13:42:32 -0700 (PDT) Received: by 10.25.37.67 with HTTP; Tue, 26 Aug 2014 13:42:32 -0700 (PDT) Date: Tue, 26 Aug 2014 13:42:32 -0700 Message-ID: Subject: ixgbe IXGBE_LEGACY_TX breaks build (patch/fix included) From: Nick Rogers To: "freebsd-net@freebsd.org" Content-Type: text/plain; charset=UTF-8 X-Content-Filtered-By: Mailman/MimeDel 2.1.18-1 Cc: jfv@freebsd.org X-BeenThere: freebsd-net@freebsd.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: Networking and TCP/IP with FreeBSD List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 26 Aug 2014 20:42:35 -0000 Hello, I am trying to get the ixgbe driver + PF/ALTQ working under stable/9. Initially, loading a PF rulset with ALTQ enabled fails on an ix interface, reporting "ix0: driver does not support altq". This is similar to the behavior over the last few years when dealing with the igb driver. However, I have been using ALTQ + igb with great success by defining IGB_LEGACY_TX in the e1000/igb driver code. I noticed that ixgbe has a similar define IXGBE_LEGACY_TX to enable the legacy, non-multiqueue transmit behavior, that also "enables" ALTQ support. After adding the IXGBE_LEGACY_TX define to ixgbe source, building the driver fails with the following compile errors: /usr/src/sys/dev/ixgbe/ixgbe.c: In function 'ixgbe_msix_que': /usr/src/sys/dev/ixgbe/ixgbe.c:1529: error: invalid type argument of '->' (have 'struct ifaltq') /usr/src/sys/dev/ixgbe/ixgbe.c:1529: error: invalid type argument of '->' (have 'struct ifaltq') /usr/src/sys/dev/ixgbe/ixgbe.c: In function 'ixgbe_local_timer': /usr/src/sys/dev/ixgbe/ixgbe.c:2077: error: 'struct tx_ring' has no member named 'txq_task' /usr/src/sys/dev/ixgbe/ixgbe.c: In function 'ixgbe_free_transmit_buffers': /usr/src/sys/dev/ixgbe/ixgbe.c:3255: error: 'struct tx_ring' has no member named 'br' /usr/src/sys/dev/ixgbe/ixgbe.c:3256: error: 'struct tx_ring' has no member named 'br' So it seems that the IXGBE_LEGACY_TX path no longer compiles successfully, and perhaps never did? Using e1000 as a reference, fixing the pointer error, and looking at previous revisions of ixgbe.c, I was able to come up with the following patch that got the driver to compile while having IXGBE_LEGACY_TX defined. Note that the following svn diff is against HEAD, which as far as I can tell contains the same broken IXGBE_LEGACY_TX path as stable/9 and stable/10. Index: ixgbe.c =================================================================== --- ixgbe.c (revision 270665) +++ ixgbe.c (working copy) @@ -1543,7 +1543,7 @@ IXGBE_TX_LOCK(txr); ixgbe_txeof(txr); #ifdef IXGBE_LEGACY_TX - if (!IFQ_DRV_IS_EMPTY(ifp->if_snd)) + if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) ixgbe_start_locked(txr, ifp); #else if (!drbr_empty(ifp, txr->br)) @@ -2091,7 +2091,11 @@ (paused == 0)) ++hung; else if (txr->queue_status == IXGBE_QUEUE_WORKING) +#ifndef IXGBE_LEGACY_TX taskqueue_enqueue(que->tq, &txr->txq_task); +#else + taskqueue_enqueue(que->tq, &que->que_task); +#endif } /* Only truely watchdog if all queues show hung */ if (hung == adapter->num_queues) @@ -3327,10 +3331,6 @@ tx_buffer->map = NULL; } } -#ifdef IXGBE_LEGACY_TX - if (txr->br != NULL) - buf_ring_free(txr->br, M_DEVBUF); -#endif if (txr->tx_buffers != NULL) { free(txr->tx_buffers, M_DEVBUF); txr->tx_buffers = NULL; =================================================================== Using a stable/9 kernel with the above patch allowed me to load my PF ruleset on a machine with an ixgbe interface and ALTQ enabled. i.e. I no longer received the "driver does not support altq error". Queueing on the ix interface now appears to work as it should. I am hoping someone can help verify my work and perhaps audit and correct the IXGBE_LEGACY_TX path currently in the svn tree. Also, FWIW, here is relevant pciconf output for the ixbge card. ix0@pci0:1:0:0: class=0x020000 card=0x00038086 chip=0x10fb8086 rev=0x01 hdr=0x00 vendor = 'Intel Corporation' device = '82599EB 10-Gigabit SFI/SFP+ Network Connection' class = network subclass = ethernet cap 01[40] = powerspec 3 supports D0 D3 current D0 cap 05[50] = MSI supports 1 message, 64 bit, vector masks cap 11[70] = MSI-X supports 64 messages in map 0x20 enabled cap 10[a0] = PCI-Express 2 endpoint max data 128(512) link x8(x8) ecap 0001[100] = AER 1 0 fatal 0 non-fatal 1 corrected ecap 0003[140] = Serial 1 0023faffff300715 ecap 000e[150] = unknown 1 ecap 0010[160] = unknown 1 ix1@pci0:1:0:1: class=0x020000 card=0x00038086 chip=0x10fb8086 rev=0x01 hdr=0x00 vendor = 'Intel Corporation' device = '82599EB 10-Gigabit SFI/SFP+ Network Connection' class = network subclass = ethernet cap 01[40] = powerspec 3 supports D0 D3 current D0 cap 05[50] = MSI supports 1 message, 64 bit, vector masks cap 11[70] = MSI-X supports 64 messages in map 0x20 enabled cap 10[a0] = PCI-Express 2 endpoint max data 128(512) link x8(x8) ecap 0001[100] = AER 1 0 fatal 0 non-fatal 1 corrected ecap 0003[140] = Serial 1 0023faffff300715 ecap 000e[150] = unknown 1 ecap 0010[160] = unknown 1 Thanks! -Nick