Date: Wed, 24 May 2006 15:02:49 +0300 (EEST) From: Andriy Gapon <avg@icyb.net.ua> To: FreeBSD-gnats-submit@FreeBSD.org Subject: i386/97785: with nforce2 chipset lapic timer can stop resulting in total system freeze - H/W problem Message-ID: <200605241202.k4OC2nXW004268@oddity.topspin.kiev.ua> Resent-Message-ID: <200605241210.k4OCAHfp044221@freefall.freebsd.org>
next in thread | raw e-mail | index | archive | help
>Number: 97785 >Category: i386 >Synopsis: with nforce2 chipset lapic timer can stop resulting in total system freeze - H/W problem >Confidential: no >Severity: serious >Priority: high >Responsible: freebsd-i386 >State: open >Quarter: >Keywords: >Date-Required: >Class: sw-bug >Submitter-Id: current-users >Arrival-Date: Wed May 24 12:10:16 GMT 2006 >Closed-Date: >Last-Modified: >Originator: Andriy Gapon >Release: FreeBSD 6.1-RELEASE i386 >Organization: >Environment: System: FreeBSD 6.1-RELEASE i386 Motherboard: nforce2-based NF-7 (v2) CPU: UP Athlon BIOS: version 2.7 (latest as of time of writing) BIOS settings: C1 CPU Disconnect is enabled; APIC is enabled Kernel: UP, device apic >Description: There is a hardware problem with nForce2 chipset that can lead to LAPIC timer being stopped if power-saving "C1 CPU Disconnect" feature is enabled. See the following link for information from nVidia: http://lkml.org/lkml/2004/5/3/157 Pre-6 UP systems do not use LAPIC timer and thus are not affected. The fix is to change PCI configuration of the chipset. Thanks to John Baldwin for creating the attached patch. For additional discussion please take a look at: http://docs.freebsd.org/cgi/getmsg.cgi?fetch=11429+0+archive/2006/freebsd-acpi/20060521.freebsd-acpi >How-To-Repeat: on nForce2 enabled system with FreeBSD 6.1+: 1. enable APIC in BIOS 2. enable C1 CPU Disconnect in BIOS or use a program like fvcool 3. boot with generic kernel 4. (optional: run fvcool; see step 2) 5. observe complete system freeze >Fix: the following patch to sys/dev/pci/fixup_pci.c adds some code to change PCI configuration according to information from nVidia. Please add this patch to HEAD, RELENG_6 and RELENG_6_1 if possible. --- fixup_pci.c.jb.patch begins here --- Index: fixup_pci.c =================================================================== RCS file: /usr/cvs/src/sys/dev/pci/fixup_pci.c,v retrieving revision 1.6 diff -u -r1.6 fixup_pci.c --- fixup_pci.c 30 May 2004 17:57:41 -0000 1.6 +++ fixup_pci.c 19 May 2006 15:14:26 -0000 @@ -51,6 +51,7 @@ static int fixup_pci_probe(device_t dev); static void fixwsc_natoma(device_t dev); +static void fixc1_nforce2(device_t dev); static device_method_t fixup_pci_methods[] = { /* Device interface */ @@ -76,6 +77,9 @@ case 0x12378086: /* Intel 82440FX (Natoma) */ fixwsc_natoma(dev); break; + case 0x01e010de: /* nVidia nForce2 */ + fixc1_nforce2(dev); + break; } return(ENXIO); } @@ -100,3 +104,37 @@ } #endif } + +/* + * Set the SYSTEM_IDLE_TIMEOUT to 80 ns on nForce2 systems to work + * around a hang that is triggered when the CPU generates a very fast + * CONNECT/HALT cycle sequence. Specifically, the hang can result in + * the lapic timer being stopped. + * + * This requires changing the value for config register at offset 0x6c + * for the Host-PCI bridge at bus/dev/function 0/0/0: + * + * Chip Current Value New Value + * ---- ---------- ---------- + * C17 0x1F0FFF01 0x1F01FF01 + * C18D 0x9F0FFF01 0x9F01FF01 + * + * We do this by always clearing the bits in 0x000e0000. + * + * See also: http://lkml.org/lkml/2004/5/3/157 + */ +static void +fixc1_nforce2(device_t dev) +{ + uint32_t val; + + if (pci_get_bus(dev) == 0 && pci_get_slot(dev) == 0 && + pci_get_function(dev) == 0) { + val = pci_read_config(dev, 0x6c, 4); + if (val & 0x000e0000) { + printf("Correcting nForce2 C1 CPU disconnect hangs\n"); + val &= ~0x000e0000; + pci_write_config(dev, 0x6c, val, 4); + } + } +} --- fixup_pci.c.jb.patch ends here --- >Release-Note: >Audit-Trail: >Unformatted:
Want to link to this message? Use this URL: <https://mail-archive.FreeBSD.org/cgi/mid.cgi?200605241202.k4OC2nXW004268>