Date: Mon, 8 Feb 2016 18:48:12 +0000 (UTC) From: Niclas Zeising <zeising@FreeBSD.org> To: ports-committers@freebsd.org, svn-ports-all@freebsd.org, svn-ports-head@freebsd.org Subject: svn commit: r408496 - head/cad/iverilog Message-ID: <201602081848.u18ImCf5092281@repo.freebsd.org>
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Author: zeising Date: Mon Feb 8 18:48:12 2016 New Revision: 408496 URL: https://svnweb.freebsd.org/changeset/ports/408496 Log: Update to 10.1 Modified: head/cad/iverilog/Makefile head/cad/iverilog/distinfo Modified: head/cad/iverilog/Makefile ============================================================================== --- head/cad/iverilog/Makefile Mon Feb 8 18:41:55 2016 (r408495) +++ head/cad/iverilog/Makefile Mon Feb 8 18:48:12 2016 (r408496) @@ -2,7 +2,7 @@ # $FreeBSD$ PORTNAME= iverilog -PORTVERSION= 10.0 +PORTVERSION= 10.1 CATEGORIES= cad MASTER_SITES= ftp://icarus.com/pub/eda/verilog/v${PORTVERSION:C,\.[0-9]$,,}/ DISTNAME= verilog-${PORTVERSION} Modified: head/cad/iverilog/distinfo ============================================================================== --- head/cad/iverilog/distinfo Mon Feb 8 18:41:55 2016 (r408495) +++ head/cad/iverilog/distinfo Mon Feb 8 18:48:12 2016 (r408496) @@ -1,2 +1,2 @@ -SHA256 (verilog-10.0.tar.gz) = 179f09afbafb951bea28c9001b06ed8b9b2e54181092d48e343cb20f436b1185 -SIZE (verilog-10.0.tar.gz) = 1683102 +SHA256 (verilog-10.1.tar.gz) = e822f397e3b7a496c8138c2b05b4209eb47b74370bc173a91c293fa8e809e529 +SIZE (verilog-10.1.tar.gz) = 1685176
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