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Date:      Sun, 11 Mar 2012 06:17:50 +0000 (UTC)
From:      Juli Mallett <jmallett@FreeBSD.org>
To:        src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org
Subject:   svn commit: r232812 - in head/sys: contrib/octeon-sdk contrib/octeon-sdk/cvmx-malloc contrib/octeon-sdk/libfdt mips/cavium mips/cavium/octe mips/cavium/usb
Message-ID:  <201203110617.q2B6Hohx096832@svn.freebsd.org>

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Author: jmallett
Date: Sun Mar 11 06:17:49 2012
New Revision: 232812
URL: http://svn.freebsd.org/changeset/base/232812

Log:
  Merge the Cavium Octeon SDK 2.3.0 Simple Executive code and update FreeBSD to
  make use of it where possible.
  
  This primarily brings in support for newer hardware, and FreeBSD is not yet
  able to support the abundance of IRQs on new hardware and many features in the
  Ethernet driver.
  
  Because of the changes to IRQs in the Simple Executive, we have to maintain our
  own list of Octeon IRQs now, which probably can be pared-down and be specific
  to the CIU interrupt unit soon, and when other interrupt mechanisms are added
  they can maintain their own definitions.
  
  Remove unmasking of interrupts from within the UART device now that the
  function used is no longer present in the Simple Executive.  The unmasking
  seems to have been gratuitous as this is more properly handled by the buses
  above the UART device, and seems to work on that basis.

Added:
  head/sys/contrib/octeon-sdk/README.txt
     - copied unchanged from r232809, vendor-sys/octeon-sdk/dist/README.txt
  head/sys/contrib/octeon-sdk/cvmx-ciu2-defs.h
     - copied unchanged from r232809, vendor-sys/octeon-sdk/dist/cvmx-ciu2-defs.h
  head/sys/contrib/octeon-sdk/cvmx-endor-defs.h
     - copied unchanged from r232809, vendor-sys/octeon-sdk/dist/cvmx-endor-defs.h
  head/sys/contrib/octeon-sdk/cvmx-eoi-defs.h
     - copied unchanged from r232809, vendor-sys/octeon-sdk/dist/cvmx-eoi-defs.h
  head/sys/contrib/octeon-sdk/cvmx-error-init-cn61xx.c
     - copied, changed from r232809, vendor-sys/octeon-sdk/dist/cvmx-error-init-cn61xx.c
  head/sys/contrib/octeon-sdk/cvmx-error-init-cn66xx.c
     - copied, changed from r232809, vendor-sys/octeon-sdk/dist/cvmx-error-init-cn66xx.c
  head/sys/contrib/octeon-sdk/cvmx-error-init-cn68xx.c
     - copied, changed from r232809, vendor-sys/octeon-sdk/dist/cvmx-error-init-cn68xx.c
  head/sys/contrib/octeon-sdk/cvmx-error-init-cn68xxp1.c
     - copied, changed from r232809, vendor-sys/octeon-sdk/dist/cvmx-error-init-cn68xxp1.c
  head/sys/contrib/octeon-sdk/cvmx-error-init-cnf71xx.c
     - copied, changed from r232809, vendor-sys/octeon-sdk/dist/cvmx-error-init-cnf71xx.c
  head/sys/contrib/octeon-sdk/cvmx-helper-cfg.c
     - copied, changed from r232809, vendor-sys/octeon-sdk/dist/cvmx-helper-cfg.c
  head/sys/contrib/octeon-sdk/cvmx-helper-cfg.h
     - copied unchanged from r232809, vendor-sys/octeon-sdk/dist/cvmx-helper-cfg.h
  head/sys/contrib/octeon-sdk/cvmx-helper-ilk.c
     - copied, changed from r232809, vendor-sys/octeon-sdk/dist/cvmx-helper-ilk.c
  head/sys/contrib/octeon-sdk/cvmx-helper-ilk.h
     - copied unchanged from r232809, vendor-sys/octeon-sdk/dist/cvmx-helper-ilk.h
  head/sys/contrib/octeon-sdk/cvmx-hfa.c
     - copied unchanged from r232809, vendor-sys/octeon-sdk/dist/cvmx-hfa.c
  head/sys/contrib/octeon-sdk/cvmx-hfa.h
     - copied unchanged from r232809, vendor-sys/octeon-sdk/dist/cvmx-hfa.h
  head/sys/contrib/octeon-sdk/cvmx-ilk-defs.h
     - copied unchanged from r232809, vendor-sys/octeon-sdk/dist/cvmx-ilk-defs.h
  head/sys/contrib/octeon-sdk/cvmx-ilk.c
     - copied, changed from r232809, vendor-sys/octeon-sdk/dist/cvmx-ilk.c
  head/sys/contrib/octeon-sdk/cvmx-ilk.h
     - copied unchanged from r232809, vendor-sys/octeon-sdk/dist/cvmx-ilk.h
  head/sys/contrib/octeon-sdk/cvmx-iob1-defs.h
     - copied unchanged from r232809, vendor-sys/octeon-sdk/dist/cvmx-iob1-defs.h
  head/sys/contrib/octeon-sdk/cvmx-ipd.c
     - copied, changed from r232809, vendor-sys/octeon-sdk/dist/cvmx-ipd.c
  head/sys/contrib/octeon-sdk/cvmx-malloc/
     - copied from r232809, vendor-sys/octeon-sdk/dist/cvmx-malloc/
  head/sys/contrib/octeon-sdk/cvmx-profiler.c
     - copied unchanged from r232809, vendor-sys/octeon-sdk/dist/cvmx-profiler.c
  head/sys/contrib/octeon-sdk/cvmx-profiler.h
     - copied unchanged from r232809, vendor-sys/octeon-sdk/dist/cvmx-profiler.h
  head/sys/contrib/octeon-sdk/cvmx-qlm-tables.c
     - copied, changed from r232809, vendor-sys/octeon-sdk/dist/cvmx-qlm-tables.c
  head/sys/contrib/octeon-sdk/cvmx-qlm.c
     - copied, changed from r232809, vendor-sys/octeon-sdk/dist/cvmx-qlm.c
  head/sys/contrib/octeon-sdk/cvmx-qlm.h
     - copied unchanged from r232809, vendor-sys/octeon-sdk/dist/cvmx-qlm.h
  head/sys/contrib/octeon-sdk/cvmx-resources.config
     - copied unchanged from r232809, vendor-sys/octeon-sdk/dist/cvmx-resources.config
  head/sys/contrib/octeon-sdk/cvmx-shared-linux-n32.ld
     - copied unchanged from r232809, vendor-sys/octeon-sdk/dist/cvmx-shared-linux-n32.ld
  head/sys/contrib/octeon-sdk/cvmx-shared-linux-o32.ld
     - copied unchanged from r232809, vendor-sys/octeon-sdk/dist/cvmx-shared-linux-o32.ld
  head/sys/contrib/octeon-sdk/cvmx-shared-linux.ld
     - copied unchanged from r232809, vendor-sys/octeon-sdk/dist/cvmx-shared-linux.ld
  head/sys/contrib/octeon-sdk/cvmx-sso-defs.h
     - copied unchanged from r232809, vendor-sys/octeon-sdk/dist/cvmx-sso-defs.h
  head/sys/contrib/octeon-sdk/cvmx-trax-defs.h
     - copied unchanged from r232809, vendor-sys/octeon-sdk/dist/cvmx-trax-defs.h
  head/sys/contrib/octeon-sdk/cvmx.mk
     - copied unchanged from r232809, vendor-sys/octeon-sdk/dist/cvmx.mk
  head/sys/contrib/octeon-sdk/executive-config.h.template
     - copied unchanged from r232809, vendor-sys/octeon-sdk/dist/executive-config.h.template
  head/sys/contrib/octeon-sdk/libfdt/
     - copied from r232809, vendor-sys/octeon-sdk/dist/libfdt/
  head/sys/contrib/octeon-sdk/octeon-feature.c
     - copied unchanged from r232809, vendor-sys/octeon-sdk/dist/octeon-feature.c
  head/sys/mips/cavium/octeon_irq.h   (contents, props changed)
Modified:
  head/sys/contrib/octeon-sdk/cvmip.h
  head/sys/contrib/octeon-sdk/cvmx-abi.h
  head/sys/contrib/octeon-sdk/cvmx-access-native.h
  head/sys/contrib/octeon-sdk/cvmx-access.h
  head/sys/contrib/octeon-sdk/cvmx-address.h
  head/sys/contrib/octeon-sdk/cvmx-agl-defs.h
  head/sys/contrib/octeon-sdk/cvmx-app-hotplug.c
  head/sys/contrib/octeon-sdk/cvmx-app-hotplug.h
  head/sys/contrib/octeon-sdk/cvmx-app-init-linux.c
  head/sys/contrib/octeon-sdk/cvmx-app-init.c
  head/sys/contrib/octeon-sdk/cvmx-app-init.h
  head/sys/contrib/octeon-sdk/cvmx-asm.h
  head/sys/contrib/octeon-sdk/cvmx-asx0-defs.h
  head/sys/contrib/octeon-sdk/cvmx-asxx-defs.h
  head/sys/contrib/octeon-sdk/cvmx-atomic.h
  head/sys/contrib/octeon-sdk/cvmx-bootloader.h
  head/sys/contrib/octeon-sdk/cvmx-bootmem.c
  head/sys/contrib/octeon-sdk/cvmx-bootmem.h
  head/sys/contrib/octeon-sdk/cvmx-ciu-defs.h
  head/sys/contrib/octeon-sdk/cvmx-clock.c
  head/sys/contrib/octeon-sdk/cvmx-clock.h
  head/sys/contrib/octeon-sdk/cvmx-cmd-queue.c
  head/sys/contrib/octeon-sdk/cvmx-cmd-queue.h
  head/sys/contrib/octeon-sdk/cvmx-cn3010-evb-hs5.c
  head/sys/contrib/octeon-sdk/cvmx-cn3010-evb-hs5.h
  head/sys/contrib/octeon-sdk/cvmx-compactflash.c
  head/sys/contrib/octeon-sdk/cvmx-compactflash.h
  head/sys/contrib/octeon-sdk/cvmx-core.c
  head/sys/contrib/octeon-sdk/cvmx-core.h
  head/sys/contrib/octeon-sdk/cvmx-coremask.c
  head/sys/contrib/octeon-sdk/cvmx-coremask.h
  head/sys/contrib/octeon-sdk/cvmx-crypto.c
  head/sys/contrib/octeon-sdk/cvmx-crypto.h
  head/sys/contrib/octeon-sdk/cvmx-csr-db-support.c
  head/sys/contrib/octeon-sdk/cvmx-csr-db.c
  head/sys/contrib/octeon-sdk/cvmx-csr-db.h
  head/sys/contrib/octeon-sdk/cvmx-csr-enums.h
  head/sys/contrib/octeon-sdk/cvmx-csr-typedefs.h
  head/sys/contrib/octeon-sdk/cvmx-csr.h
  head/sys/contrib/octeon-sdk/cvmx-dbg-defs.h
  head/sys/contrib/octeon-sdk/cvmx-debug-handler.S
  head/sys/contrib/octeon-sdk/cvmx-debug-remote.c
  head/sys/contrib/octeon-sdk/cvmx-debug-uart.c
  head/sys/contrib/octeon-sdk/cvmx-debug.c
  head/sys/contrib/octeon-sdk/cvmx-debug.h
  head/sys/contrib/octeon-sdk/cvmx-dfa-defs.h
  head/sys/contrib/octeon-sdk/cvmx-dfa.c
  head/sys/contrib/octeon-sdk/cvmx-dfa.h
  head/sys/contrib/octeon-sdk/cvmx-dfm-defs.h
  head/sys/contrib/octeon-sdk/cvmx-dma-engine.c
  head/sys/contrib/octeon-sdk/cvmx-dma-engine.h
  head/sys/contrib/octeon-sdk/cvmx-dpi-defs.h
  head/sys/contrib/octeon-sdk/cvmx-ebt3000.c
  head/sys/contrib/octeon-sdk/cvmx-ebt3000.h
  head/sys/contrib/octeon-sdk/cvmx-error-custom.c
  head/sys/contrib/octeon-sdk/cvmx-error-custom.h
  head/sys/contrib/octeon-sdk/cvmx-error-init-cn30xx.c
  head/sys/contrib/octeon-sdk/cvmx-error-init-cn31xx.c
  head/sys/contrib/octeon-sdk/cvmx-error-init-cn38xx.c
  head/sys/contrib/octeon-sdk/cvmx-error-init-cn38xxp2.c
  head/sys/contrib/octeon-sdk/cvmx-error-init-cn50xx.c
  head/sys/contrib/octeon-sdk/cvmx-error-init-cn52xx.c
  head/sys/contrib/octeon-sdk/cvmx-error-init-cn52xxp1.c
  head/sys/contrib/octeon-sdk/cvmx-error-init-cn56xx.c
  head/sys/contrib/octeon-sdk/cvmx-error-init-cn56xxp1.c
  head/sys/contrib/octeon-sdk/cvmx-error-init-cn58xx.c
  head/sys/contrib/octeon-sdk/cvmx-error-init-cn58xxp1.c
  head/sys/contrib/octeon-sdk/cvmx-error-init-cn63xx.c
  head/sys/contrib/octeon-sdk/cvmx-error-init-cn63xxp1.c
  head/sys/contrib/octeon-sdk/cvmx-error.c
  head/sys/contrib/octeon-sdk/cvmx-error.h
  head/sys/contrib/octeon-sdk/cvmx-fau.h
  head/sys/contrib/octeon-sdk/cvmx-flash.c
  head/sys/contrib/octeon-sdk/cvmx-flash.h
  head/sys/contrib/octeon-sdk/cvmx-fpa-defs.h
  head/sys/contrib/octeon-sdk/cvmx-fpa.c
  head/sys/contrib/octeon-sdk/cvmx-fpa.h
  head/sys/contrib/octeon-sdk/cvmx-gmx.h
  head/sys/contrib/octeon-sdk/cvmx-gmxx-defs.h
  head/sys/contrib/octeon-sdk/cvmx-gpio-defs.h
  head/sys/contrib/octeon-sdk/cvmx-gpio.h
  head/sys/contrib/octeon-sdk/cvmx-helper-board.c
  head/sys/contrib/octeon-sdk/cvmx-helper-board.h
  head/sys/contrib/octeon-sdk/cvmx-helper-check-defines.h
  head/sys/contrib/octeon-sdk/cvmx-helper-errata.c
  head/sys/contrib/octeon-sdk/cvmx-helper-errata.h
  head/sys/contrib/octeon-sdk/cvmx-helper-fpa.c
  head/sys/contrib/octeon-sdk/cvmx-helper-fpa.h
  head/sys/contrib/octeon-sdk/cvmx-helper-jtag.c
  head/sys/contrib/octeon-sdk/cvmx-helper-jtag.h
  head/sys/contrib/octeon-sdk/cvmx-helper-loop.c
  head/sys/contrib/octeon-sdk/cvmx-helper-loop.h
  head/sys/contrib/octeon-sdk/cvmx-helper-npi.c
  head/sys/contrib/octeon-sdk/cvmx-helper-npi.h
  head/sys/contrib/octeon-sdk/cvmx-helper-rgmii.c
  head/sys/contrib/octeon-sdk/cvmx-helper-rgmii.h
  head/sys/contrib/octeon-sdk/cvmx-helper-sgmii.c
  head/sys/contrib/octeon-sdk/cvmx-helper-sgmii.h
  head/sys/contrib/octeon-sdk/cvmx-helper-spi.c
  head/sys/contrib/octeon-sdk/cvmx-helper-spi.h
  head/sys/contrib/octeon-sdk/cvmx-helper-srio.c
  head/sys/contrib/octeon-sdk/cvmx-helper-srio.h
  head/sys/contrib/octeon-sdk/cvmx-helper-util.c
  head/sys/contrib/octeon-sdk/cvmx-helper-util.h
  head/sys/contrib/octeon-sdk/cvmx-helper-xaui.c
  head/sys/contrib/octeon-sdk/cvmx-helper-xaui.h
  head/sys/contrib/octeon-sdk/cvmx-helper.c
  head/sys/contrib/octeon-sdk/cvmx-helper.h
  head/sys/contrib/octeon-sdk/cvmx-higig.h
  head/sys/contrib/octeon-sdk/cvmx-interrupt-handler.S
  head/sys/contrib/octeon-sdk/cvmx-interrupt.c
  head/sys/contrib/octeon-sdk/cvmx-interrupt.h
  head/sys/contrib/octeon-sdk/cvmx-iob-defs.h
  head/sys/contrib/octeon-sdk/cvmx-ipd-defs.h
  head/sys/contrib/octeon-sdk/cvmx-ipd.h
  head/sys/contrib/octeon-sdk/cvmx-ixf18201.c
  head/sys/contrib/octeon-sdk/cvmx-ixf18201.h
  head/sys/contrib/octeon-sdk/cvmx-key-defs.h
  head/sys/contrib/octeon-sdk/cvmx-key.h
  head/sys/contrib/octeon-sdk/cvmx-l2c-defs.h
  head/sys/contrib/octeon-sdk/cvmx-l2c.c
  head/sys/contrib/octeon-sdk/cvmx-l2c.h
  head/sys/contrib/octeon-sdk/cvmx-l2d-defs.h
  head/sys/contrib/octeon-sdk/cvmx-l2t-defs.h
  head/sys/contrib/octeon-sdk/cvmx-led-defs.h
  head/sys/contrib/octeon-sdk/cvmx-llm.c
  head/sys/contrib/octeon-sdk/cvmx-llm.h
  head/sys/contrib/octeon-sdk/cvmx-lmcx-defs.h
  head/sys/contrib/octeon-sdk/cvmx-log-arc.S
  head/sys/contrib/octeon-sdk/cvmx-log.c
  head/sys/contrib/octeon-sdk/cvmx-log.h
  head/sys/contrib/octeon-sdk/cvmx-malloc.h
  head/sys/contrib/octeon-sdk/cvmx-mdio.h
  head/sys/contrib/octeon-sdk/cvmx-mgmt-port.c
  head/sys/contrib/octeon-sdk/cvmx-mgmt-port.h
  head/sys/contrib/octeon-sdk/cvmx-mio-defs.h
  head/sys/contrib/octeon-sdk/cvmx-mixx-defs.h
  head/sys/contrib/octeon-sdk/cvmx-mpi-defs.h
  head/sys/contrib/octeon-sdk/cvmx-nand.c
  head/sys/contrib/octeon-sdk/cvmx-nand.h
  head/sys/contrib/octeon-sdk/cvmx-ndf-defs.h
  head/sys/contrib/octeon-sdk/cvmx-npei-defs.h
  head/sys/contrib/octeon-sdk/cvmx-npi-defs.h
  head/sys/contrib/octeon-sdk/cvmx-npi.h
  head/sys/contrib/octeon-sdk/cvmx-packet.h
  head/sys/contrib/octeon-sdk/cvmx-pci-defs.h
  head/sys/contrib/octeon-sdk/cvmx-pci.h
  head/sys/contrib/octeon-sdk/cvmx-pcie.c
  head/sys/contrib/octeon-sdk/cvmx-pcie.h
  head/sys/contrib/octeon-sdk/cvmx-pcieepx-defs.h
  head/sys/contrib/octeon-sdk/cvmx-pciercx-defs.h
  head/sys/contrib/octeon-sdk/cvmx-pcm-defs.h
  head/sys/contrib/octeon-sdk/cvmx-pcmx-defs.h
  head/sys/contrib/octeon-sdk/cvmx-pcsx-defs.h
  head/sys/contrib/octeon-sdk/cvmx-pcsxx-defs.h
  head/sys/contrib/octeon-sdk/cvmx-pemx-defs.h
  head/sys/contrib/octeon-sdk/cvmx-pescx-defs.h
  head/sys/contrib/octeon-sdk/cvmx-pexp-defs.h
  head/sys/contrib/octeon-sdk/cvmx-pip-defs.h
  head/sys/contrib/octeon-sdk/cvmx-pip.h
  head/sys/contrib/octeon-sdk/cvmx-pko-defs.h
  head/sys/contrib/octeon-sdk/cvmx-pko.c
  head/sys/contrib/octeon-sdk/cvmx-pko.h
  head/sys/contrib/octeon-sdk/cvmx-platform.h
  head/sys/contrib/octeon-sdk/cvmx-pow-defs.h
  head/sys/contrib/octeon-sdk/cvmx-pow.c
  head/sys/contrib/octeon-sdk/cvmx-pow.h
  head/sys/contrib/octeon-sdk/cvmx-power-throttle.c
  head/sys/contrib/octeon-sdk/cvmx-power-throttle.h
  head/sys/contrib/octeon-sdk/cvmx-rad-defs.h
  head/sys/contrib/octeon-sdk/cvmx-raid.c
  head/sys/contrib/octeon-sdk/cvmx-raid.h
  head/sys/contrib/octeon-sdk/cvmx-rng.h
  head/sys/contrib/octeon-sdk/cvmx-rnm-defs.h
  head/sys/contrib/octeon-sdk/cvmx-rtc.h
  head/sys/contrib/octeon-sdk/cvmx-rwlock.h
  head/sys/contrib/octeon-sdk/cvmx-scratch.h
  head/sys/contrib/octeon-sdk/cvmx-shmem.c
  head/sys/contrib/octeon-sdk/cvmx-shmem.h
  head/sys/contrib/octeon-sdk/cvmx-sim-magic.h
  head/sys/contrib/octeon-sdk/cvmx-sli-defs.h
  head/sys/contrib/octeon-sdk/cvmx-smi-defs.h
  head/sys/contrib/octeon-sdk/cvmx-smix-defs.h
  head/sys/contrib/octeon-sdk/cvmx-spi.c
  head/sys/contrib/octeon-sdk/cvmx-spi.h
  head/sys/contrib/octeon-sdk/cvmx-spi4000.c
  head/sys/contrib/octeon-sdk/cvmx-spinlock.h
  head/sys/contrib/octeon-sdk/cvmx-spx0-defs.h
  head/sys/contrib/octeon-sdk/cvmx-spxx-defs.h
  head/sys/contrib/octeon-sdk/cvmx-srio.c
  head/sys/contrib/octeon-sdk/cvmx-srio.h
  head/sys/contrib/octeon-sdk/cvmx-sriomaintx-defs.h
  head/sys/contrib/octeon-sdk/cvmx-sriox-defs.h
  head/sys/contrib/octeon-sdk/cvmx-srxx-defs.h
  head/sys/contrib/octeon-sdk/cvmx-stxx-defs.h
  head/sys/contrib/octeon-sdk/cvmx-swap.h
  head/sys/contrib/octeon-sdk/cvmx-sysinfo.c
  head/sys/contrib/octeon-sdk/cvmx-sysinfo.h
  head/sys/contrib/octeon-sdk/cvmx-thunder.c
  head/sys/contrib/octeon-sdk/cvmx-thunder.h
  head/sys/contrib/octeon-sdk/cvmx-tim-defs.h
  head/sys/contrib/octeon-sdk/cvmx-tim.c
  head/sys/contrib/octeon-sdk/cvmx-tim.h
  head/sys/contrib/octeon-sdk/cvmx-tlb.c
  head/sys/contrib/octeon-sdk/cvmx-tlb.h
  head/sys/contrib/octeon-sdk/cvmx-tra-defs.h
  head/sys/contrib/octeon-sdk/cvmx-tra.c
  head/sys/contrib/octeon-sdk/cvmx-tra.h
  head/sys/contrib/octeon-sdk/cvmx-twsi.c
  head/sys/contrib/octeon-sdk/cvmx-twsi.h
  head/sys/contrib/octeon-sdk/cvmx-uahcx-defs.h
  head/sys/contrib/octeon-sdk/cvmx-uart.c
  head/sys/contrib/octeon-sdk/cvmx-uart.h
  head/sys/contrib/octeon-sdk/cvmx-uctlx-defs.h
  head/sys/contrib/octeon-sdk/cvmx-usb.c
  head/sys/contrib/octeon-sdk/cvmx-usb.h
  head/sys/contrib/octeon-sdk/cvmx-usbcx-defs.h
  head/sys/contrib/octeon-sdk/cvmx-usbd.c
  head/sys/contrib/octeon-sdk/cvmx-usbd.h
  head/sys/contrib/octeon-sdk/cvmx-usbnx-defs.h
  head/sys/contrib/octeon-sdk/cvmx-utils.h
  head/sys/contrib/octeon-sdk/cvmx-version.h
  head/sys/contrib/octeon-sdk/cvmx-warn.c
  head/sys/contrib/octeon-sdk/cvmx-warn.h
  head/sys/contrib/octeon-sdk/cvmx-wqe.h
  head/sys/contrib/octeon-sdk/cvmx-zip-defs.h
  head/sys/contrib/octeon-sdk/cvmx-zip.c
  head/sys/contrib/octeon-sdk/cvmx-zip.h
  head/sys/contrib/octeon-sdk/cvmx-zone.c
  head/sys/contrib/octeon-sdk/cvmx.h
  head/sys/contrib/octeon-sdk/octeon-boot-info.h
  head/sys/contrib/octeon-sdk/octeon-feature.h
  head/sys/contrib/octeon-sdk/octeon-model.c
  head/sys/contrib/octeon-sdk/octeon-model.h
  head/sys/contrib/octeon-sdk/octeon-pci-console.c
  head/sys/contrib/octeon-sdk/octeon-pci-console.h
  head/sys/mips/cavium/ciu.c
  head/sys/mips/cavium/files.octeon1
  head/sys/mips/cavium/if_octm.c
  head/sys/mips/cavium/obio.c
  head/sys/mips/cavium/octe/ethernet-rgmii.c
  head/sys/mips/cavium/octe/ethernet-rx.c
  head/sys/mips/cavium/octe/ethernet-spi.c
  head/sys/mips/cavium/octe/ethernet.c
  head/sys/mips/cavium/octe/wrapper-cvmx-includes.h
  head/sys/mips/cavium/octeon_gpio.c
  head/sys/mips/cavium/octeon_machdep.c
  head/sys/mips/cavium/octeon_mp.c
  head/sys/mips/cavium/octeon_wdog.c
  head/sys/mips/cavium/octopci.c
  head/sys/mips/cavium/uart_dev_oct16550.c
  head/sys/mips/cavium/usb/octusb_octeon.c
Directory Properties:
  head/sys/contrib/octeon-sdk/   (props changed)

Copied: head/sys/contrib/octeon-sdk/README.txt (from r232809, vendor-sys/octeon-sdk/dist/README.txt)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ head/sys/contrib/octeon-sdk/README.txt	Sun Mar 11 06:17:49 2012	(r232812, copy of r232809, vendor-sys/octeon-sdk/dist/README.txt)
@@ -0,0 +1,43 @@
+Readme for the OCTEON Executive Library
+
+
+The OCTEON Executive Library provides runtime support and hardware 
+abstraction for the OCTEON processor.  The executive is composed of the 
+libcvmx.a library as well as header files that provide  
+functionality with inline functions.
+
+
+Usage:
+
+The libcvmx.a library is built for every application as part of the
+application build. (Please refer to the 'related pages' section of the 
+HTML documentation for more information on the build system.)  
+Applications using the executive should include the header files from
+$OCTEON_ROOT/target/include and link against the library that is built in 
+the local obj directory. Each file using the executive 
+should include the following two header files in order:
+
+#include "cvmx-config.h"
+#include "cvmx.h"
+
+The cvmx-config.h file contains configuration information for the 
+executive and is generated by the cvmx-config script from an 
+'executive-config.h' file. A sample version of this file is provided 
+in the executive directory as 'executive-config.h.template'.  
+
+Copy this file to 'executive-config.h' into the 'config' subdirectory 
+of the application directory and customize as required by the application. 
+Applications that don't use any simple executive functionality can omit 
+the cvmx-config.h header file. Please refer to the examples for a 
+demonstration of where to put the executive-config.h file and for an
+example of generated cvmx-config.h.
+
+For file specific information please see the documentation within the 
+source files or the HTML documentation provided in docs/html/index.html.
+The HTML documentation is automatically generated by Doxygen from the 
+source files.
+
+
+
+==========================================================================
+Please see the release notes for version specific information.

Modified: head/sys/contrib/octeon-sdk/cvmip.h
==============================================================================
--- head/sys/contrib/octeon-sdk/cvmip.h	Sun Mar 11 06:11:31 2012	(r232811)
+++ head/sys/contrib/octeon-sdk/cvmip.h	Sun Mar 11 06:17:49 2012	(r232812)
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -46,11 +46,11 @@
 /**
  * @file
  *
- * Cavium Networks Internet Protocol (IP)
+ * Cavium Inc. Internet Protocol (IP)
  *
  * Definitions for the Internet Protocol (IP) support.
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  *
  */
 

Modified: head/sys/contrib/octeon-sdk/cvmx-abi.h
==============================================================================
--- head/sys/contrib/octeon-sdk/cvmx-abi.h	Sun Mar 11 06:11:31 2012	(r232811)
+++ head/sys/contrib/octeon-sdk/cvmx-abi.h	Sun Mar 11 06:17:49 2012	(r232812)
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -39,21 +39,25 @@
 
 
 
-
-
-
-
 /**
  * @file
  *
  * This file defines macros for use in determining the current calling ABI.
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
 */
 
 #ifndef __CVMX_ABI_H__
 #define __CVMX_ABI_H__
 
+#if defined(__FreeBSD__) && defined(_KERNEL)
+#include <machine/endian.h>
+#else
+#ifndef __U_BOOT__
+#include <endian.h>
+#endif
+#endif
+
 #ifdef	__cplusplus
 extern "C" {
 #endif
@@ -87,6 +91,20 @@ extern "C" {
     #endif
 #endif
 
+/* For compatibility with Linux definitions... */
+#if __BYTE_ORDER == __BIG_ENDIAN
+# ifndef __BIG_ENDIAN_BITFIELD
+#  define __BIG_ENDIAN_BITFIELD
+# endif
+#else
+# ifndef __LITTLE_ENDIAN_BITFIELD
+#  define __LITTLE_ENDIAN_BITFIELD
+# endif
+#endif
+#if defined(__BIG_ENDIAN_BITFIELD) && defined(__LITTLE_ENDIAN_BITFIELD)
+# error Cannot define both __BIG_ENDIAN_BITFIELD and __LITTLE_ENDIAN_BITFIELD
+#endif
+
 #ifdef	__cplusplus
 }
 #endif

Modified: head/sys/contrib/octeon-sdk/cvmx-access-native.h
==============================================================================
--- head/sys/contrib/octeon-sdk/cvmx-access-native.h	Sun Mar 11 06:11:31 2012	(r232811)
+++ head/sys/contrib/octeon-sdk/cvmx-access-native.h	Sun Mar 11 06:17:49 2012	(r232812)
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -183,12 +183,6 @@ static inline void *cvmx_phys_to_ptr(uin
         cvmx_warn_if(physical_address==0, "cvmx_phys_to_ptr() passed a zero address\n");
 
 #ifdef CVMX_BUILD_FOR_UBOOT
-#if !CONFIG_OCTEON_UBOOT_TLB
-    if (physical_address >= 0x80000000)
-        return NULL;
-    else
-        return CASTPTR(void, (physical_address & 0x7FFFFFFF));
-#endif
 
     /* U-boot is a special case, as it is running in 32 bit mode, using the TLB to map code/data
     ** which can have a physical address above the 32 bit address space.  1-1 mappings are used
@@ -251,8 +245,9 @@ static inline void *cvmx_phys_to_ptr(uin
         2nd 256MB is mapped at 0x10000000 and the rest of memory is 1:1 */
     if ((physical_address >= 0x10000000) && (physical_address < 0x20000000))
         return CASTPTR(void, CVMX_ADD_SEG32(CVMX_MIPS32_SPACE_KSEG0, physical_address));
-    else if (!OCTEON_IS_MODEL(OCTEON_CN6XXX) && (physical_address >= 0x410000000ull) &&
-                                                       (physical_address < 0x420000000ull))
+    else if ((OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX))
+              && (physical_address >= 0x410000000ull)
+              && (physical_address < 0x420000000ull))
         return CASTPTR(void, physical_address - 0x400000000ull);
     else
         return CASTPTR(void, physical_address);

Modified: head/sys/contrib/octeon-sdk/cvmx-access.h
==============================================================================
--- head/sys/contrib/octeon-sdk/cvmx-access.h	Sun Mar 11 06:11:31 2012	(r232811)
+++ head/sys/contrib/octeon-sdk/cvmx-access.h	Sun Mar 11 06:17:49 2012	(r232812)
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM

Modified: head/sys/contrib/octeon-sdk/cvmx-address.h
==============================================================================
--- head/sys/contrib/octeon-sdk/cvmx-address.h	Sun Mar 11 06:11:31 2012	(r232811)
+++ head/sys/contrib/octeon-sdk/cvmx-address.h	Sun Mar 11 06:17:49 2012	(r232812)
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -47,6 +47,10 @@
 #ifndef __CVMX_ADDRESS_H__
 #define __CVMX_ADDRESS_H__
 
+#ifndef CVMX_BUILD_FOR_LINUX_KERNEL
+#include "cvmx-abi.h"
+#endif
+
 #ifdef	__cplusplus
 extern "C" {
 #endif
@@ -233,6 +237,7 @@ typedef union {
 #define CVMX_OCT_DID_TAG_TAG2       CVMX_FULL_DID(CVMX_OCT_DID_TAG,2ULL)
 #define CVMX_OCT_DID_TAG_TAG3       CVMX_FULL_DID(CVMX_OCT_DID_TAG,3ULL)
 #define CVMX_OCT_DID_TAG_NULL_RD    CVMX_FULL_DID(CVMX_OCT_DID_TAG,4ULL)
+#define CVMX_OCT_DID_TAG_TAG5       CVMX_FULL_DID(CVMX_OCT_DID_TAG,5ULL)
 #define CVMX_OCT_DID_TAG_CSR        CVMX_FULL_DID(CVMX_OCT_DID_TAG,7ULL)
 #define CVMX_OCT_DID_FAU_FAI        CVMX_FULL_DID(CVMX_OCT_DID_IOB,0ULL)
 #define CVMX_OCT_DID_TIM_CSR        CVMX_FULL_DID(CVMX_OCT_DID_TIM,0ULL)
@@ -245,6 +250,14 @@ typedef union {
 #define CVMX_OCT_DID_MIS_CSR        CVMX_FULL_DID(CVMX_OCT_DID_MIS,7ULL)
 #define CVMX_OCT_DID_ZIP_CSR        CVMX_FULL_DID(CVMX_OCT_DID_ZIP,0ULL)
 
+#ifndef CVMX_BUILD_FOR_LINUX_KERNEL
+#ifdef CVMX_ABI_N32
+#define UNMAPPED_PTR(x) ( (1U << 31) | x )
+#else
+#define UNMAPPED_PTR(x) ( (1ULL << 63) | x )
+#endif
+#endif
+
 #ifdef	__cplusplus
 }
 #endif

Modified: head/sys/contrib/octeon-sdk/cvmx-agl-defs.h
==============================================================================
--- head/sys/contrib/octeon-sdk/cvmx-agl-defs.h	Sun Mar 11 06:11:31 2012	(r232811)
+++ head/sys/contrib/octeon-sdk/cvmx-agl-defs.h	Sun Mar 11 06:17:49 2012	(r232812)
@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -49,14 +49,14 @@
  * <hr>$Revision$<hr>
  *
  */
-#ifndef __CVMX_AGL_TYPEDEFS_H__
-#define __CVMX_AGL_TYPEDEFS_H__
+#ifndef __CVMX_AGL_DEFS_H__
+#define __CVMX_AGL_DEFS_H__
 
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 #define CVMX_AGL_GMX_BAD_REG CVMX_AGL_GMX_BAD_REG_FUNC()
 static inline uint64_t CVMX_AGL_GMX_BAD_REG_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
 		cvmx_warn("CVMX_AGL_GMX_BAD_REG not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011800E0000518ull);
 }
@@ -67,7 +67,7 @@ static inline uint64_t CVMX_AGL_GMX_BAD_
 #define CVMX_AGL_GMX_BIST CVMX_AGL_GMX_BIST_FUNC()
 static inline uint64_t CVMX_AGL_GMX_BIST_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
 		cvmx_warn("CVMX_AGL_GMX_BIST not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011800E0000400ull);
 }
@@ -102,7 +102,10 @@ static inline uint64_t CVMX_AGL_GMX_PRTX
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_PRTX_CFG(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E0000010ull) + ((offset) & 1) * 2048;
 }
@@ -115,7 +118,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_RXX_ADR_CAM0(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E0000180ull) + ((offset) & 1) * 2048;
 }
@@ -128,7 +134,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_RXX_ADR_CAM1(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E0000188ull) + ((offset) & 1) * 2048;
 }
@@ -141,7 +150,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_RXX_ADR_CAM2(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E0000190ull) + ((offset) & 1) * 2048;
 }
@@ -154,7 +166,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_RXX_ADR_CAM3(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E0000198ull) + ((offset) & 1) * 2048;
 }
@@ -167,7 +182,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_RXX_ADR_CAM4(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E00001A0ull) + ((offset) & 1) * 2048;
 }
@@ -180,7 +198,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_RXX_ADR_CAM5(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E00001A8ull) + ((offset) & 1) * 2048;
 }
@@ -193,7 +214,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_RXX_ADR_CAM_EN(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E0000108ull) + ((offset) & 1) * 2048;
 }
@@ -206,7 +230,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_RXX_ADR_CTL(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E0000100ull) + ((offset) & 1) * 2048;
 }
@@ -219,7 +246,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_RXX_DECISION(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E0000040ull) + ((offset) & 1) * 2048;
 }
@@ -232,7 +262,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_RXX_FRM_CHK(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E0000020ull) + ((offset) & 1) * 2048;
 }
@@ -245,7 +278,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_RXX_FRM_CTL(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E0000018ull) + ((offset) & 1) * 2048;
 }
@@ -258,7 +294,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_RXX_FRM_MAX(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E0000030ull) + ((offset) & 1) * 2048;
 }
@@ -271,7 +310,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_RXX_FRM_MIN(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E0000028ull) + ((offset) & 1) * 2048;
 }
@@ -284,7 +326,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_RXX_IFG(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E0000058ull) + ((offset) & 1) * 2048;
 }
@@ -297,7 +342,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_RXX_INT_EN(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E0000008ull) + ((offset) & 1) * 2048;
 }
@@ -310,7 +358,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_RXX_INT_REG(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E0000000ull) + ((offset) & 1) * 2048;
 }
@@ -323,7 +374,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_RXX_JABBER(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E0000038ull) + ((offset) & 1) * 2048;
 }
@@ -336,7 +390,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_RXX_PAUSE_DROP_TIME(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E0000068ull) + ((offset) & 1) * 2048;
 }
@@ -347,7 +404,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_
 static inline uint64_t CVMX_AGL_GMX_RXX_RX_INBND(unsigned long offset)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_RXX_RX_INBND(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E0000060ull) + ((offset) & 1) * 2048;
 }
@@ -360,7 +420,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_RXX_STATS_CTL(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E0000050ull) + ((offset) & 1) * 2048;
 }
@@ -373,7 +436,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_RXX_STATS_OCTS(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E0000088ull) + ((offset) & 1) * 2048;
 }
@@ -386,7 +452,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_RXX_STATS_OCTS_CTL(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E0000098ull) + ((offset) & 1) * 2048;
 }
@@ -399,7 +468,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_RXX_STATS_OCTS_DMAC(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E00000A8ull) + ((offset) & 1) * 2048;
 }
@@ -412,7 +484,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_RXX_STATS_OCTS_DRP(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E00000B8ull) + ((offset) & 1) * 2048;
 }
@@ -425,7 +500,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_RXX_STATS_PKTS(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E0000080ull) + ((offset) & 1) * 2048;
 }
@@ -438,7 +516,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_RXX_STATS_PKTS_BAD(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E00000C0ull) + ((offset) & 1) * 2048;
 }
@@ -451,7 +532,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_RXX_STATS_PKTS_CTL(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E0000090ull) + ((offset) & 1) * 2048;
 }
@@ -464,7 +548,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_RXX_STATS_PKTS_DMAC(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E00000A0ull) + ((offset) & 1) * 2048;
 }
@@ -477,7 +564,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_RXX_STATS_PKTS_DRP(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E00000B0ull) + ((offset) & 1) * 2048;
 }
@@ -490,7 +580,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_RXX_UDD_SKP(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E0000048ull) + ((offset) & 1) * 2048;
 }
@@ -503,7 +596,10 @@ static inline uint64_t CVMX_AGL_GMX_RX_B
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_RX_BP_DROPX(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E0000420ull) + ((offset) & 1) * 8;
 }
@@ -516,7 +612,10 @@ static inline uint64_t CVMX_AGL_GMX_RX_B
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_RX_BP_OFFX(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E0000460ull) + ((offset) & 1) * 8;
 }
@@ -529,7 +628,10 @@ static inline uint64_t CVMX_AGL_GMX_RX_B
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_RX_BP_ONX(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E0000440ull) + ((offset) & 1) * 8;
 }
@@ -540,7 +642,7 @@ static inline uint64_t CVMX_AGL_GMX_RX_B
 #define CVMX_AGL_GMX_RX_PRT_INFO CVMX_AGL_GMX_RX_PRT_INFO_FUNC()
 static inline uint64_t CVMX_AGL_GMX_RX_PRT_INFO_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
 		cvmx_warn("CVMX_AGL_GMX_RX_PRT_INFO not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011800E00004E8ull);
 }
@@ -551,7 +653,7 @@ static inline uint64_t CVMX_AGL_GMX_RX_P
 #define CVMX_AGL_GMX_RX_TX_STATUS CVMX_AGL_GMX_RX_TX_STATUS_FUNC()
 static inline uint64_t CVMX_AGL_GMX_RX_TX_STATUS_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
 		cvmx_warn("CVMX_AGL_GMX_RX_TX_STATUS not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011800E00007E8ull);
 }
@@ -564,7 +666,10 @@ static inline uint64_t CVMX_AGL_GMX_SMAC
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_SMACX(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E0000230ull) + ((offset) & 1) * 2048;
 }
@@ -575,7 +680,7 @@ static inline uint64_t CVMX_AGL_GMX_SMAC
 #define CVMX_AGL_GMX_STAT_BP CVMX_AGL_GMX_STAT_BP_FUNC()
 static inline uint64_t CVMX_AGL_GMX_STAT_BP_FUNC(void)
 {
-	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
 		cvmx_warn("CVMX_AGL_GMX_STAT_BP not supported on this chip\n");
 	return CVMX_ADD_IO_SEG(0x00011800E0000520ull);
 }
@@ -588,7 +693,10 @@ static inline uint64_t CVMX_AGL_GMX_TXX_
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_TXX_APPEND(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E0000218ull) + ((offset) & 1) * 2048;
 }
@@ -599,7 +707,10 @@ static inline uint64_t CVMX_AGL_GMX_TXX_
 static inline uint64_t CVMX_AGL_GMX_TXX_CLK(unsigned long offset)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_TXX_CLK(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E0000208ull) + ((offset) & 1) * 2048;
 }
@@ -612,7 +723,10 @@ static inline uint64_t CVMX_AGL_GMX_TXX_
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_TXX_CTL(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E0000270ull) + ((offset) & 1) * 2048;
 }
@@ -625,7 +739,10 @@ static inline uint64_t CVMX_AGL_GMX_TXX_
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_TXX_MIN_PKT(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E0000240ull) + ((offset) & 1) * 2048;
 }
@@ -638,7 +755,10 @@ static inline uint64_t CVMX_AGL_GMX_TXX_
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_TXX_PAUSE_PKT_INTERVAL(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E0000248ull) + ((offset) & 1) * 2048;
 }
@@ -651,7 +771,10 @@ static inline uint64_t CVMX_AGL_GMX_TXX_
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_TXX_PAUSE_PKT_TIME(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E0000238ull) + ((offset) & 1) * 2048;
 }
@@ -664,7 +787,10 @@ static inline uint64_t CVMX_AGL_GMX_TXX_
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_TXX_PAUSE_TOGO(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E0000258ull) + ((offset) & 1) * 2048;
 }
@@ -677,7 +803,10 @@ static inline uint64_t CVMX_AGL_GMX_TXX_
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_TXX_PAUSE_ZERO(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E0000260ull) + ((offset) & 1) * 2048;
 }
@@ -690,7 +819,10 @@ static inline uint64_t CVMX_AGL_GMX_TXX_
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_TXX_SOFT_PAUSE(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E0000250ull) + ((offset) & 1) * 2048;
 }
@@ -703,7 +835,10 @@ static inline uint64_t CVMX_AGL_GMX_TXX_
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_TXX_STAT0(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E0000280ull) + ((offset) & 1) * 2048;
 }
@@ -716,7 +851,10 @@ static inline uint64_t CVMX_AGL_GMX_TXX_
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_TXX_STAT1(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E0000288ull) + ((offset) & 1) * 2048;
 }
@@ -729,7 +867,10 @@ static inline uint64_t CVMX_AGL_GMX_TXX_
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_TXX_STAT2(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E0000290ull) + ((offset) & 1) * 2048;
 }
@@ -742,7 +883,10 @@ static inline uint64_t CVMX_AGL_GMX_TXX_
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_TXX_STAT3(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E0000298ull) + ((offset) & 1) * 2048;
 }
@@ -755,7 +899,10 @@ static inline uint64_t CVMX_AGL_GMX_TXX_
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_TXX_STAT4(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E00002A0ull) + ((offset) & 1) * 2048;
 }
@@ -768,7 +915,10 @@ static inline uint64_t CVMX_AGL_GMX_TXX_
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_TXX_STAT5(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E00002A8ull) + ((offset) & 1) * 2048;
 }
@@ -781,7 +931,10 @@ static inline uint64_t CVMX_AGL_GMX_TXX_
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 		cvmx_warn("CVMX_AGL_GMX_TXX_STAT6(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00011800E00002B0ull) + ((offset) & 1) * 2048;
 }
@@ -794,7 +947,10 @@ static inline uint64_t CVMX_AGL_GMX_TXX_

*** DIFF OUTPUT TRUNCATED AT 1000 LINES ***



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