Date: Wed, 11 Aug 2010 19:10:00 +0200 From: Attilio Rao <attilio@freebsd.org> To: Kostik Belousov <kostikbel@gmail.com> Cc: svn-src-head@freebsd.org, svn-src-all@freebsd.org, src-committers@freebsd.org, Jeff Roberson <jeff@freebsd.org>, John Baldwin <jhb@freebsd.org> Subject: Re: svn commit: r211176 - in head/sys: amd64/amd64 i386/i386 Message-ID: <AANLkTi=qDOGFWnKfH63vRF1Hx-_cc1Z0H71Vm2bMM-ti@mail.gmail.com> In-Reply-To: <AANLkTimvkEkP_08jNU_YyS%2BeDOcQtFf6xwiE2Xfscd5v@mail.gmail.com> References: <201008111051.o7BApRp4028538@svn.freebsd.org> <20100811105739.GJ2396@deviant.kiev.zoral.com.ua> <AANLkTikk3m-=5W7TVV5C-XM4AnwS1LuAi7GGEeP0B9dV@mail.gmail.com> <20100811123430.GK2396@deviant.kiev.zoral.com.ua> <AANLkTikmSTt7jLPMfFeSxyTi00KfvuWCHCL5XBZouf2m@mail.gmail.com> <20100811144646.GL2396@deviant.kiev.zoral.com.ua> <AANLkTimvkEkP_08jNU_YyS%2BeDOcQtFf6xwiE2Xfscd5v@mail.gmail.com>
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2010/8/11 Attilio Rao <attilio@freebsd.org>: > 2010/8/11 Kostik Belousov <kostikbel@gmail.com>: >> On Wed, Aug 11, 2010 at 04:29:21PM +0200, Attilio Rao wrote: >>> 2010/8/11 Kostik Belousov <kostikbel@gmail.com>: >>> > On Wed, Aug 11, 2010 at 01:21:46PM +0200, Attilio Rao wrote: >>> >> 2010/8/11 Kostik Belousov <kostikbel@gmail.com>: >>> >> > On Wed, Aug 11, 2010 at 10:51:27AM +0000, Attilio Rao wrote: >>> >> >> Author: attilio >>> >> >> Date: Wed Aug 11 10:51:27 2010 >>> >> >> New Revision: 211176 >>> >> >> URL: http://svn.freebsd.org/changeset/base/211176 >>> >> >> >>> >> >> Log: >>> >> >> =C2=A0 IPI handlers may run generally with interrupts disabled be= cause they >>> >> >> =C2=A0 are served via an interrupt gate. >>> >> >> >>> >> >> =C2=A0 However, that doesn't explicitly prevent preemption and th= read >>> >> >> =C2=A0 migration thus scheduler pinning may be necessary in some = handlers. >>> >> >> =C2=A0 Fix that. >>> >> > >>> >> > How the preemption is supposed to happen ? Aside from the explicit >>> >> > calls to mi_switch() from e.g. critical_exit(). >>> >> >>> >> IIRC it should be hardclock() willing to schedule the softclock(). I= t >>> >> is the critical_exit() in the thread_unlock() that may trigger it >>> >> (sorry for not digging more, it was a while back that I hacked this >>> >> part, but I guess you can verify on your own). >>> >> We already have other points within the kernel that take care of >>> >> dealing with preemption/migration like lapic_handle_timer(), for >>> >> example. >>> > >>> > Right, and if the interrupts are indeed disabled, I do not see how >>> > the preemption may be triggered in the fragments like >>> > =C2=A0 =C2=A0 =C2=A0 =C2=A0cpu =3D PCPU_GET(cpuid); >>> > =C2=A0 =C2=A0 =C2=A0 =C2=A0cpumask =3D PCPU_GET(cpumask); >>> >>> I don't recall all the details and I have no time to dig now. However, >>> also spinlock_enter() does disable explicitly preemption via >>> critical_enter() after have disabled the interrupts. >>> Let me CC jhb as he implemented spinlock_enter() and may have a clue >>> about how preemption can happen with interrupts disabled. >> >> spinlock_enter() disables preemption to handle the recursive >> calls to spinlock_enter/leave, I think, to prevent switch on >> leave. > > No. > Please look at how spinlock_enter() is implemented in ia32/amd64 in > order to see how it does handle recursion. And besides we have other patterns running with interrupts disabled taking care of preemption as well (I think I already pointed to one, I think you could find others easilly). Attilio --=20 Peace can only be achieved by understanding - A. Einstein
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