From owner-svn-src-all@FreeBSD.ORG Fri Feb 18 08:00:27 2011 Return-Path: Delivered-To: svn-src-all@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 20D9710656B8; Fri, 18 Feb 2011 08:00:27 +0000 (UTC) (envelope-from np@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:4f8:fff6::2c]) by mx1.freebsd.org (Postfix) with ESMTP id 0D2CC8FC12; Fri, 18 Feb 2011 08:00:27 +0000 (UTC) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.3/8.14.3) with ESMTP id p1I80Rge047728; Fri, 18 Feb 2011 08:00:27 GMT (envelope-from np@svn.freebsd.org) Received: (from np@localhost) by svn.freebsd.org (8.14.3/8.14.3/Submit) id p1I80QGt047717; Fri, 18 Feb 2011 08:00:26 GMT (envelope-from np@svn.freebsd.org) Message-Id: <201102180800.p1I80QGt047717@svn.freebsd.org> From: Navdeep Parhar Date: Fri, 18 Feb 2011 08:00:26 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Subject: svn commit: r218792 - in head: share/man/man4 sys/conf sys/dev/cxgbe sys/dev/cxgbe/common sys/modules sys/modules/cxgbe usr.sbin/sysinstall X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 18 Feb 2011 08:00:27 -0000 Author: np Date: Fri Feb 18 08:00:26 2011 New Revision: 218792 URL: http://svn.freebsd.org/changeset/base/218792 Log: cxgbe(4) - NIC driver for Chelsio T4 (Terminator 4) based 10Gb/1Gb adapters. MFC after: 3 weeks Added: head/share/man/man4/cxgbe.4 (contents, props changed) head/sys/dev/cxgbe/ head/sys/dev/cxgbe/adapter.h (contents, props changed) head/sys/dev/cxgbe/common/ head/sys/dev/cxgbe/common/common.h (contents, props changed) head/sys/dev/cxgbe/common/t4_hw.c (contents, props changed) head/sys/dev/cxgbe/common/t4_hw.h (contents, props changed) head/sys/dev/cxgbe/common/t4_msg.h (contents, props changed) head/sys/dev/cxgbe/common/t4_regs.h (contents, props changed) head/sys/dev/cxgbe/common/t4_regs_values.h (contents, props changed) head/sys/dev/cxgbe/common/t4_tcb.h (contents, props changed) head/sys/dev/cxgbe/common/t4fw_interface.h (contents, props changed) head/sys/dev/cxgbe/offload.h (contents, props changed) head/sys/dev/cxgbe/osdep.h (contents, props changed) head/sys/dev/cxgbe/t4_ioctl.h (contents, props changed) head/sys/dev/cxgbe/t4_main.c (contents, props changed) head/sys/dev/cxgbe/t4_sge.c (contents, props changed) head/sys/modules/cxgbe/ head/sys/modules/cxgbe/Makefile (contents, props changed) Modified: head/share/man/man4/Makefile head/share/man/man4/altq.4 head/share/man/man4/vlan.4 head/sys/conf/NOTES head/sys/conf/files head/sys/conf/kern.pre.mk head/sys/modules/Makefile head/usr.sbin/sysinstall/devices.c Modified: head/share/man/man4/Makefile ============================================================================== --- head/share/man/man4/Makefile Fri Feb 18 07:37:30 2011 (r218791) +++ head/share/man/man4/Makefile Fri Feb 18 08:00:26 2011 (r218792) @@ -83,6 +83,7 @@ MAN= aac.4 \ crypto.4 \ cue.4 \ cxgb.4 \ + cxgbe.4 \ cy.4 \ da.4 \ dc.4 \ Modified: head/share/man/man4/altq.4 ============================================================================== --- head/share/man/man4/altq.4 Fri Feb 18 07:37:30 2011 (r218791) +++ head/share/man/man4/altq.4 Fri Feb 18 08:00:26 2011 (r218792) @@ -127,6 +127,7 @@ They have been applied to the following .Xr bfe 4 , .Xr bge 4 , .Xr cas 4 , +.Xr cxgbe 4 , .Xr dc 4 , .Xr de 4 , .Xr ed 4 , Added: head/share/man/man4/cxgbe.4 ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ head/share/man/man4/cxgbe.4 Fri Feb 18 08:00:26 2011 (r218792) @@ -0,0 +1,167 @@ +.\" Copyright (c) 2011, Chelsio Inc +.\" All rights reserved. +.\" +.\" Redistribution and use in source and binary forms, with or without +.\" modification, are permitted provided that the following conditions are met: +.\" +.\" 1. Redistributions of source code must retain the above copyright notice, +.\" this list of conditions and the following disclaimer. +.\" +.\" 2. Redistributions in binary form must reproduce the above copyright +.\" notice, this list of conditions and the following disclaimer in the +.\" documentation and/or other materials provided with the distribution. +.\" +.\" 3. Neither the name of the Chelsio Inc nor the names of its +.\" contributors may be used to endorse or promote products derived from +.\" this software without specific prior written permission. +.\" +.\" THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +.\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +.\" ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +.\" LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +.\" CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +.\" SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +.\" INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +.\" CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +.\" ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +.\" POSSIBILITY OF SUCH DAMAGE. +.\" +.\" * Other names and brands may be claimed as the property of others. +.\" +.\" $FreeBSD$ +.\" +.Dd February 14, 2011 +.Dt CXGBE 4 +.Os +.Sh NAME +.Nm cxgbe +.Nd "Chelsio T4 10Gb and 1Gb Ethernet adapter driver" +.Sh SYNOPSIS +To compile this driver into the kernel, +place the following lines in your +kernel configuration file: +.Bd -ragged -offset indent +.Cd "device cxgbe" +.Ed +.Pp +To load the driver as a +module at boot time, place the following line in +.Xr loader.conf 5 : +.Bd -literal -offset indent +if_cxgbe_load="YES" +.Ed +.Sh DESCRIPTION +The +.Nm +driver provides support for PCI Express Ethernet adapters based on +the Chelsio Terminator 4 (T4) ASIC. +The driver supprts Jumbo Frames, Transmit/Receive checksum offload, +TCP segmentation offload (TSO), Large Receive Offload (LRO), VLAN +tag insertion/extraction, VLAN checksum offload, VLAN TSO, and +Receive Side Steering (RSS). + +For further hardware information and questions related to hardware +requirements, see +.Pa http://www.chelsio.com/ . +.Pp +For more information on configuring this device, see +.Xr ifconfig 8 . +.Sh HARDWARE +The +.Nm +driver supports 10Gb and 1Gb Ethernet adapters based on the T4 ASIC: +.Pp +.Bl -bullet -compact +.It +Chelsio T420-CR +.It +Chelsio T422-CR +.It +Chelsio T440-CR +.It +Chelsio T420-BCH +.It +Chelsio T440-BCH +.It +Chelsio T440-CH +.It +Chelsio T420-SO +.It +Chelsio T420-CX +.It +Chelsio T420-BT +.It +Chelsio T404-BT +.El +.Sh LOADER TUNABLES +Tunables can be set at the +.Xr loader 8 +prompt before booting the kernel or stored in +.Xr loader.conf 5 . +.Bl -tag -width indent +.It Va hw.cxgbe.max_ntxq_10G_port +The maximum number of tx queues to use for a 10Gb port. +The default value is 8. +.It Va hw.cxgbe.max_nrxq_10G_port +The maximum number of rx queues to use for a 10Gb port. +The default value is 8. +.It Va hw.cxgbe.max_ntxq_1G_port +The maximum number of tx queues to use for a 1Gb port. +The default value is 2. +.It Va hw.cxgbe.max_nrxq_1G_port +The maximum number of rx queues to use for a 1Gb port. +The default value is 2. +.It Va hw.cxgbe.holdoff_timer_idx_10G +.It Va hw.cxgbe.holdoff_timer_idx_1G +The timer index value to use to delay interrupts. +The holdoff timer list has the values 1, 5, 10, 50, 100, and 200 +by default (all values are in microseconds) and the index selects a +value from this list. +The default value is 1 for both 10Gb and 1Gb ports, which means the +timer value is 5us. +.It Va hw.cxgbe.holdoff_pktc_idx_10G +.It Va hw.cxgbe.holdoff_pktc_idx_1G +The packet-count index value to use to delay interrupts. +The packet-count list has the values 1, 8, 16, and 32 by default +and the index selects a value from this list. +The default value is 2 for both 10Gb and 1Gb ports, which means 16 +packets (or the holdoff timer going off) before an interrupt is +generated. +.It Va hw.cxgbe.qsize_txq +The size, in number of entries, of the descriptor ring used for a tx +queue. +A buf_ring of the same size is also allocated for additional +software queuing. See +.Xr ifnet 9 . +The default value is 1024. +.It Va hw.cxgbe.qsize_rxq +The size, in number of entries, of the descriptor ring used for an +rx queue. +The default value is 1024. +.Sh SUPPORT +For general information and support, +go to the Chelsio support website at: +.Pa http://www.chelsio.com/ . +.Pp +If an issue is identified with this driver with a supported adapter, +email all the specific information related to the issue to +.Aq support@chelsio.com . +.Sh SEE ALSO +.Xr altq 4 , +.Xr arp 4 , +.Xr cxgb 4 , +.Xr netintro 4 , +.Xr ng_ether 4 , +.Xr ifconfig 8 +.Sh HISTORY +The +.Nm +device driver first appeared in +.Fx 9.0 +.Sh AUTHORS +.An -nosplit +The +.Nm +driver was written by +.An Navdeep Parhar Aq np@FreeBSD.org . Modified: head/share/man/man4/vlan.4 ============================================================================== --- head/share/man/man4/vlan.4 Fri Feb 18 07:37:30 2011 (r218791) +++ head/share/man/man4/vlan.4 Fri Feb 18 08:00:26 2011 (r218792) @@ -128,6 +128,7 @@ in the hardware is limited to the follow .Xr bce 4 , .Xr bge 4 , .Xr cxgb 4 , +.Xr cxgbe 4 , .Xr em 4 , .Xr igb 4 , .Xr ixgb 4 , Modified: head/sys/conf/NOTES ============================================================================== --- head/sys/conf/NOTES Fri Feb 18 07:37:30 2011 (r218791) +++ head/sys/conf/NOTES Fri Feb 18 08:00:26 2011 (r218792) @@ -1902,6 +1902,8 @@ device xmphy # XaQti XMAC II # cas: Sun Cassini/Cassini+ and National Semiconductor DP83065 Saturn # cm: Arcnet SMC COM90c26 / SMC COM90c56 # (and SMC COM90c66 in '56 compatibility mode) adapters. +# cxgbe: Support for PCI express 10Gb/1Gb adapters based on the Chelsio T4 +# (Terminator 4) ASIC. # dc: Support for PCI fast ethernet adapters based on the DEC/Intel 21143 # and various workalikes including: # the ADMtek AL981 Comet and AN985 Centaur, the ASIX Electronics @@ -2073,6 +2075,7 @@ device wb # Winbond W89C840F device xl # 3Com 3c90x (``Boomerang'', ``Cyclone'') # PCI Ethernet NICs. +device cxgbe # Chelsio T4 10GbE PCIe adapter device de # DEC/Intel DC21x4x (``Tulip'') device em # Intel Pro/1000 Gigabit Ethernet device igb # Intel Pro/1000 PCIE Gigabit Ethernet Modified: head/sys/conf/files ============================================================================== --- head/sys/conf/files Fri Feb 18 07:37:30 2011 (r218791) +++ head/sys/conf/files Fri Feb 18 08:00:26 2011 (r218792) @@ -853,6 +853,12 @@ dev/cxgb/sys/uipc_mvec.c optional cxgb p compile-with "${NORMAL_C} -I$S/dev/cxgb" dev/cxgb/cxgb_t3fw.c optional cxgb cxgb_t3fw \ compile-with "${NORMAL_C} -I$S/dev/cxgb" +dev/cxgbe/t4_main.c optional cxgbe pci \ + compile-with "${NORMAL_C} -I$S/dev/cxgbe" +dev/cxgbe/t4_sge.c optional cxgbe pci \ + compile-with "${NORMAL_C} -I$S/dev/cxgbe" +dev/cxgbe/common/t4_hw.c optional cxgbe pci \ + compile-with "${NORMAL_C} -I$S/dev/cxgbe" dev/cy/cy.c optional cy dev/cy/cy_isa.c optional cy isa dev/cy/cy_pci.c optional cy pci Modified: head/sys/conf/kern.pre.mk ============================================================================== --- head/sys/conf/kern.pre.mk Fri Feb 18 07:37:30 2011 (r218791) +++ head/sys/conf/kern.pre.mk Fri Feb 18 08:00:26 2011 (r218792) @@ -82,8 +82,8 @@ INCLUDES+= -I$S/dev/twa # ... and XFS INCLUDES+= -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs -# ... and the same for cxgb -INCLUDES+= -I$S/dev/cxgb +# ... and the same for cxgb and cxgbe +INCLUDES+= -I$S/dev/cxgb -I$S/dev/cxgbe .endif Added: head/sys/dev/cxgbe/adapter.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ head/sys/dev/cxgbe/adapter.h Fri Feb 18 08:00:26 2011 (r218792) @@ -0,0 +1,569 @@ +/*- + * Copyright (c) 2011 Chelsio Communications, Inc. + * All rights reserved. + * Written by: Navdeep Parhar + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + * + */ + +#ifndef __T4_ADAPTER_H__ +#define __T4_ADAPTER_H__ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "offload.h" +#include "common/t4fw_interface.h" + +#define T4_FWNAME "t4fw" + +MALLOC_DECLARE(M_CXGBE); +#define CXGBE_UNIMPLEMENTED(s) \ + panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__) + +#if defined(__i386__) || defined(__amd64__) +static __inline void +prefetch(void *x) +{ + __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); +} +#else +#define prefetch(x) +#endif + +#ifdef __amd64__ +/* XXX: need systemwide bus_space_read_8/bus_space_write_8 */ +static __inline uint64_t +t4_bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle, + bus_size_t offset) +{ + KASSERT(tag == X86_BUS_SPACE_IO, + ("64-bit reads from I/O space not possible.")); + + return (*(volatile uint64_t *)(handle + offset)); +} + +static __inline void +t4_bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t bsh, + bus_size_t offset, uint64_t value) +{ + KASSERT(tag == X86_BUS_SPACE_IO, + ("64-bit writes to I/O space not possible.")); + *(volatile uint64_t *)(bsh + offset) = value; +} +#else +static __inline uint64_t +t4_bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle, + bus_size_t offset) +{ + return (uint64_t)bus_space_read_4(tag, handle, offset) + + ((uint64_t)bus_space_read_4(tag, handle, offset + 4) << 32); +} + +static __inline void +t4_bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t bsh, + bus_size_t offset, uint64_t value) +{ + bus_space_write_4(tag, bsh, offset, value); + bus_space_write_4(tag, bsh, offset + 4, value >> 32); +} +#endif + +struct adapter; +typedef struct adapter adapter_t; + +enum { + FW_IQ_QSIZE = 256, + FW_IQ_ESIZE = 64, /* At least 64 mandated by the firmware spec */ + + RX_IQ_QSIZE = 1024, + RX_IQ_ESIZE = 64, /* At least 64 so CPL_RX_PKT will fit */ + + RX_FL_ESIZE = 64, /* 8 64bit addresses */ + + FL_BUF_SIZES = 4, + + TX_EQ_QSIZE = 1024, + TX_EQ_ESIZE = 64, + TX_SGL_SEGS = 36, + TX_WR_FLITS = SGE_MAX_WR_LEN / 8 +}; + +enum { + /* adapter flags */ + FULL_INIT_DONE = (1 << 0), + FW_OK = (1 << 1), + INTR_FWD = (1 << 2), + + CXGBE_BUSY = (1 << 9), + + /* port flags */ + DOOMED = (1 << 0), + VI_ENABLED = (1 << 1), +}; + +#define IS_DOOMED(pi) (pi->flags & DOOMED) +#define SET_DOOMED(pi) do {pi->flags |= DOOMED;} while (0) +#define IS_BUSY(sc) (sc->flags & CXGBE_BUSY) +#define SET_BUSY(sc) do {sc->flags |= CXGBE_BUSY;} while (0) +#define CLR_BUSY(sc) do {sc->flags &= ~CXGBE_BUSY;} while (0) + +struct port_info { + device_t dev; + struct adapter *adapter; + + struct ifnet *ifp; + struct ifmedia media; + + struct mtx pi_lock; + char lockname[16]; + unsigned long flags; + int if_flags; + + uint16_t viid; + int16_t xact_addr_filt;/* index of exact MAC address filter */ + uint16_t rss_size; /* size of VI's RSS table slice */ + uint8_t lport; /* associated offload logical port */ + int8_t mdio_addr; + uint8_t port_type; + uint8_t mod_type; + uint8_t port_id; + uint8_t tx_chan; + + /* These need to be int as they are used in sysctl */ + int ntxq; /* # of tx queues */ + int first_txq; /* index of first tx queue */ + int nrxq; /* # of rx queues */ + int first_rxq; /* index of first rx queue */ + int tmr_idx; + int pktc_idx; + int qsize_rxq; + int qsize_txq; + + struct link_config link_cfg; + struct port_stats stats; + + struct callout tick; + struct sysctl_ctx_list ctx; /* lives from ifconfig up to down */ + struct sysctl_oid *oid_rxq; + struct sysctl_oid *oid_txq; + + uint8_t hw_addr[ETHER_ADDR_LEN]; /* factory MAC address, won't change */ +}; + +struct fl_sdesc { + struct mbuf *m; + bus_dmamap_t map; + caddr_t cl; + uint8_t tag_idx; /* the sc->fl_tag this map comes from */ +#ifdef INVARIANTS + __be64 ba_tag; +#endif +}; + +struct tx_desc { + __be64 flit[8]; +}; + +struct tx_map { + struct mbuf *m; + bus_dmamap_t map; +}; + +struct tx_sdesc { + uint8_t desc_used; /* # of hardware descriptors used by the WR */ + uint8_t map_used; /* # of frames sent out in the WR */ +}; + +typedef void (iq_intr_handler_t)(void *); + +enum { + /* iq flags */ + IQ_ALLOCATED = (1 << 1), /* firmware resources allocated */ + IQ_STARTED = (1 << 2), /* started */ +}; + +/* + * Ingress Queue: T4 is producer, driver is consumer. + */ +struct sge_iq { + bus_dma_tag_t desc_tag; + bus_dmamap_t desc_map; + struct mtx iq_lock; + char lockname[16]; + unsigned int flags; + struct adapter *adapter; + + __be64 *desc; /* KVA of descriptor ring */ + bus_addr_t ba; /* bus address of descriptor ring */ + const __be64 *cdesc; /* current descriptor */ + uint8_t gen; /* generation bit */ + uint8_t intr_params; /* interrupt holdoff parameters */ + int8_t intr_pktc_idx; /* packet count threshold index */ + uint8_t intr_next; /* holdoff for next interrupt */ + uint8_t esize; /* size (bytes) of each entry in the queue */ + uint16_t qsize; /* size (# of entries) of the queue */ + uint16_t cidx; /* consumer index */ + uint16_t cntxt_id; /* SGE context id for the iq */ + uint16_t abs_id; /* absolute SGE id for the iq */ + iq_intr_handler_t *handler; +}; + +enum { + /* eq flags */ + EQ_ALLOCATED = (1 << 1), /* firmware resources allocated */ + EQ_STARTED = (1 << 2), /* started */ + EQ_STALLED = (1 << 3), /* currently stalled */ +}; + +/* + * Egress Queue: driver is producer, T4 is consumer. + * + * Note: A free list is an egress queue (driver produces the buffers and T4 + * consumes them) but it's special enough to have its own struct (see sge_fl). + */ +struct sge_eq { + bus_dma_tag_t tx_tag; /* tag for transmit buffers */ + bus_dma_tag_t desc_tag; + bus_dmamap_t desc_map; + char lockname[16]; + unsigned int flags; + struct mtx eq_lock; + + struct tx_desc *desc; /* KVA of descriptor ring */ + bus_addr_t ba; /* bus address of descriptor ring */ + struct tx_sdesc *sdesc; /* KVA of software descriptor ring */ + struct buf_ring *br; /* tx buffer ring */ + struct sge_qstat *spg; /* status page, for convenience */ + uint16_t cap; /* max # of desc, for convenience */ + uint16_t avail; /* available descriptors, for convenience */ + uint16_t qsize; /* size (# of entries) of the queue */ + uint16_t cidx; /* consumer idx (desc idx) */ + uint16_t pidx; /* producer idx (desc idx) */ + uint16_t pending; /* # of descriptors used since last doorbell */ + uint32_t cntxt_id; /* SGE context id for the eq */ + + /* DMA maps used for tx */ + struct tx_map *maps; + uint32_t map_total; /* # of DMA maps */ + uint32_t map_pidx; /* next map to be used */ + uint32_t map_cidx; /* reclaimed up to this index */ + uint32_t map_avail; /* # of available maps */ +} __aligned(CACHE_LINE_SIZE); + +struct sge_fl { + bus_dma_tag_t desc_tag; + bus_dmamap_t desc_map; + bus_dma_tag_t tag[FL_BUF_SIZES]; + uint8_t tag_idx; + struct mtx fl_lock; + char lockname[16]; + + __be64 *desc; /* KVA of descriptor ring, ptr to addresses */ + bus_addr_t ba; /* bus address of descriptor ring */ + struct fl_sdesc *sdesc; /* KVA of software descriptor ring */ + uint32_t cap; /* max # of buffers, for convenience */ + uint16_t qsize; /* size (# of entries) of the queue */ + uint16_t cntxt_id; /* SGE context id for the freelist */ + uint32_t cidx; /* consumer idx (buffer idx, NOT hw desc idx) */ + uint32_t pidx; /* producer idx (buffer idx, NOT hw desc idx) */ + uint32_t needed; /* # of buffers needed to fill up fl. */ + uint32_t pending; /* # of bufs allocated since last doorbell */ + unsigned int dmamap_failed; +}; + +/* txq: SGE egress queue + miscellaneous items */ +struct sge_txq { + struct sge_eq eq; /* MUST be first */ + struct mbuf *m; /* held up due to temporary resource shortage */ + + /* stats for common events first */ + + uint64_t txcsum; /* # of times hardware assisted with checksum */ + uint64_t tso_wrs; /* # of IPv4 TSO work requests */ + uint64_t vlan_insertion;/* # of times VLAN tag was inserted */ + uint64_t imm_wrs; /* # of work requests with immediate data */ + uint64_t sgl_wrs; /* # of work requests with direct SGL */ + uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */ + uint64_t txpkts_wrs; /* # of coalesced tx work requests */ + uint64_t txpkts_pkts; /* # of frames in coalesced tx work requests */ + + /* stats for not-that-common events */ + + uint32_t no_dmamap; /* no DMA map to load the mbuf */ + uint32_t no_desc; /* out of hardware descriptors */ + uint32_t egr_update; /* # of SGE_EGR_UPDATE notifications for txq */ +}; + +enum { + RXQ_LRO_ENABLED = (1 << 0) +}; +/* rxq: SGE ingress queue + SGE free list + miscellaneous items */ +struct sge_rxq { + struct sge_iq iq; /* MUST be first */ + struct sge_fl fl; + + unsigned int flags; + struct port_info *port; /* the port this rxq belongs to */ + struct lro_ctrl lro; /* LRO state */ + + /* stats for common events first */ + + uint64_t rxcsum; /* # of times hardware assisted with checksum */ + uint64_t vlan_extraction;/* # of times VLAN tag was extracted */ + + /* stats for not-that-common events */ + +} __aligned(CACHE_LINE_SIZE); + +struct sge { + uint16_t timer_val[SGE_NTIMERS]; + uint8_t counter_val[SGE_NCOUNTERS]; + + int nrxq; /* total rx queues (all ports and the rest) */ + int ntxq; /* total tx queues (all ports and the rest) */ + int niq; /* total ingress queues */ + int neq; /* total egress queues */ + + struct sge_iq fwq; /* Firmware event queue */ + struct sge_iq *fiq; /* Forwarded interrupt queues (INTR_FWD) */ + struct sge_txq *txq; /* NIC tx queues */ + struct sge_rxq *rxq; /* NIC rx queues */ + + uint16_t iq_start; + int eq_start; + struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */ + struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */ +}; + +struct adapter { + device_t dev; + struct cdev *cdev; + + /* PCIe register resources */ + int regs_rid; + struct resource *regs_res; + int msix_rid; + struct resource *msix_res; + bus_space_handle_t bh; + bus_space_tag_t bt; + bus_size_t mmio_len; + + unsigned int pf; + unsigned int mbox; + + /* Interrupt information */ + int intr_type; + int intr_count; + struct irq { + struct resource *res; + int rid; + void *tag; + } *irq; + + bus_dma_tag_t dmat; /* Parent DMA tag */ + + struct sge sge; + + struct port_info *port[MAX_NPORTS]; + uint8_t chan_map[NCHAN]; + + struct tid_info tids; + + int registered_device_map; + int open_device_map; + int flags; + + char fw_version[32]; + struct adapter_params params; + struct t4_virt_res vres; + + struct mtx sc_lock; + char lockname[16]; +}; + +#define ADAPTER_LOCK(sc) mtx_lock(&(sc)->sc_lock) +#define ADAPTER_UNLOCK(sc) mtx_unlock(&(sc)->sc_lock) +#define ADAPTER_LOCK_ASSERT_OWNED(sc) mtx_assert(&(sc)->sc_lock, MA_OWNED) +#define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) mtx_assert(&(sc)->sc_lock, MA_NOTOWNED) + +#define PORT_LOCK(pi) mtx_lock(&(pi)->pi_lock) +#define PORT_UNLOCK(pi) mtx_unlock(&(pi)->pi_lock) +#define PORT_LOCK_ASSERT_OWNED(pi) mtx_assert(&(pi)->pi_lock, MA_OWNED) +#define PORT_LOCK_ASSERT_NOTOWNED(pi) mtx_assert(&(pi)->pi_lock, MA_NOTOWNED) + +#define IQ_LOCK(iq) mtx_lock(&(iq)->iq_lock) +#define IQ_UNLOCK(iq) mtx_unlock(&(iq)->iq_lock) +#define IQ_LOCK_ASSERT_OWNED(iq) mtx_assert(&(iq)->iq_lock, MA_OWNED) +#define IQ_LOCK_ASSERT_NOTOWNED(iq) mtx_assert(&(iq)->iq_lock, MA_NOTOWNED) + +#define FL_LOCK(fl) mtx_lock(&(fl)->fl_lock) +#define FL_TRYLOCK(fl) mtx_trylock(&(fl)->fl_lock) +#define FL_UNLOCK(fl) mtx_unlock(&(fl)->fl_lock) +#define FL_LOCK_ASSERT_OWNED(fl) mtx_assert(&(fl)->fl_lock, MA_OWNED) +#define FL_LOCK_ASSERT_NOTOWNED(fl) mtx_assert(&(fl)->fl_lock, MA_NOTOWNED) + +#define RXQ_LOCK(rxq) IQ_LOCK(&(rxq)->iq) +#define RXQ_UNLOCK(rxq) IQ_UNLOCK(&(rxq)->iq) +#define RXQ_LOCK_ASSERT_OWNED(rxq) IQ_LOCK_ASSERT_OWNED(&(rxq)->iq) +#define RXQ_LOCK_ASSERT_NOTOWNED(rxq) IQ_LOCK_ASSERT_NOTOWNED(&(rxq)->iq) + +#define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl) +#define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl) +#define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl) +#define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl) + +#define EQ_LOCK(eq) mtx_lock(&(eq)->eq_lock) +#define EQ_TRYLOCK(eq) mtx_trylock(&(eq)->eq_lock) +#define EQ_UNLOCK(eq) mtx_unlock(&(eq)->eq_lock) +#define EQ_LOCK_ASSERT_OWNED(eq) mtx_assert(&(eq)->eq_lock, MA_OWNED) +#define EQ_LOCK_ASSERT_NOTOWNED(eq) mtx_assert(&(eq)->eq_lock, MA_NOTOWNED) + +#define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq) +#define TXQ_TRYLOCK(txq) EQ_TRYLOCK(&(txq)->eq) +#define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq) +#define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq) +#define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq) + +#define for_each_txq(pi, iter, txq) \ + txq = &pi->adapter->sge.txq[pi->first_txq]; \ + for (iter = 0; iter < pi->ntxq; ++iter, ++txq) +#define for_each_rxq(pi, iter, rxq) \ + rxq = &pi->adapter->sge.rxq[pi->first_rxq]; \ + for (iter = 0; iter < pi->nrxq; ++iter, ++rxq) + +#define NFIQ(sc) ((sc)->intr_count > 1 ? (sc)->intr_count - 1 : 1) + +static inline uint32_t +t4_read_reg(struct adapter *sc, uint32_t reg) +{ + return bus_space_read_4(sc->bt, sc->bh, reg); +} + +static inline void +t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val) +{ + bus_space_write_4(sc->bt, sc->bh, reg, val); +} + +static inline uint64_t +t4_read_reg64(struct adapter *sc, uint32_t reg) +{ + return t4_bus_space_read_8(sc->bt, sc->bh, reg); +} + +static inline void +t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val) +{ + t4_bus_space_write_8(sc->bt, sc->bh, reg, val); +} + +static inline void +t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val) +{ + *val = pci_read_config(sc->dev, reg, 1); +} + +static inline void +t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val) +{ + pci_write_config(sc->dev, reg, val, 1); +} + +static inline void +t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val) +{ + *val = pci_read_config(sc->dev, reg, 2); +} + +static inline void +t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val) +{ + pci_write_config(sc->dev, reg, val, 2); +} + +static inline void +t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val) +{ + *val = pci_read_config(sc->dev, reg, 4); +} + +static inline void +t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val) +{ + pci_write_config(sc->dev, reg, val, 4); +} + +static inline struct port_info * +adap2pinfo(struct adapter *sc, int idx) +{ + return (sc->port[idx]); +} + +static inline void +t4_os_set_hw_addr(struct adapter *sc, int idx, uint8_t hw_addr[]) +{ + bcopy(hw_addr, sc->port[idx]->hw_addr, ETHER_ADDR_LEN); +} + +static inline bool is_10G_port(const struct port_info *pi) +{ + return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G) != 0); +} + +int t4_os_find_pci_capability(struct adapter *, int); +int t4_os_pci_save_state(struct adapter *); +int t4_os_pci_restore_state(struct adapter *); + +void t4_os_portmod_changed(const struct adapter *, int); +void t4_os_link_changed(struct adapter *, int, int); + +void t4_sge_init(struct adapter *); +int t4_create_dma_tag(struct adapter *); +int t4_destroy_dma_tag(struct adapter *); +int t4_setup_adapter_iqs(struct adapter *); +int t4_teardown_adapter_iqs(struct adapter *); +int t4_setup_eth_queues(struct port_info *); +int t4_teardown_eth_queues(struct port_info *); +void t4_intr_all(void *); +void t4_intr_fwd(void *); +void t4_intr_err(void *); +void t4_intr_evt(void *); +void t4_intr_data(void *); +int t4_eth_tx(struct ifnet *, struct sge_txq *, struct mbuf *); +void t4_update_fl_bufsize(struct ifnet *); + +#endif Added: head/sys/dev/cxgbe/common/common.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ head/sys/dev/cxgbe/common/common.h Fri Feb 18 08:00:26 2011 (r218792) @@ -0,0 +1,517 @@ +/*- + * Copyright (c) 2011 Chelsio Communications, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + * + */ + +#ifndef __CHELSIO_COMMON_H +#define __CHELSIO_COMMON_H + +#include "t4_hw.h" + + +enum { + MAX_NPORTS = 4, /* max # of ports */ + SERNUM_LEN = 24, /* Serial # length */ + EC_LEN = 16, /* E/C length */ + ID_LEN = 16, /* ID length */ +}; + +enum { MEM_EDC0, MEM_EDC1, MEM_MC }; + +enum dev_master { MASTER_CANT, MASTER_MAY, MASTER_MUST }; + +enum dev_state { DEV_STATE_UNINIT, DEV_STATE_INIT, DEV_STATE_ERR }; + +enum { + PAUSE_RX = 1 << 0, + PAUSE_TX = 1 << 1, + PAUSE_AUTONEG = 1 << 2 +}; + +#define FW_VERSION_MAJOR 1 +#define FW_VERSION_MINOR 2 +#define FW_VERSION_MICRO 65 + +struct port_stats { + u64 tx_octets; /* total # of octets in good frames */ + u64 tx_frames; /* all good frames */ + u64 tx_bcast_frames; /* all broadcast frames */ + u64 tx_mcast_frames; /* all multicast frames */ + u64 tx_ucast_frames; /* all unicast frames */ + u64 tx_error_frames; /* all error frames */ + + u64 tx_frames_64; /* # of Tx frames in a particular range */ + u64 tx_frames_65_127; + u64 tx_frames_128_255; + u64 tx_frames_256_511; + u64 tx_frames_512_1023; + u64 tx_frames_1024_1518; + u64 tx_frames_1519_max; + + u64 tx_drop; /* # of dropped Tx frames */ + u64 tx_pause; /* # of transmitted pause frames */ + u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */ + u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */ + u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */ + u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */ + u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */ + u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */ + u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */ + u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */ + + u64 rx_octets; /* total # of octets in good frames */ + u64 rx_frames; /* all good frames */ + u64 rx_bcast_frames; /* all broadcast frames */ + u64 rx_mcast_frames; /* all multicast frames */ + u64 rx_ucast_frames; /* all unicast frames */ + u64 rx_too_long; /* # of frames exceeding MTU */ + u64 rx_jabber; /* # of jabber frames */ + u64 rx_fcs_err; /* # of received frames with bad FCS */ + u64 rx_len_err; /* # of received frames with length error */ + u64 rx_symbol_err; /* symbol errors */ + u64 rx_runt; /* # of short frames */ + + u64 rx_frames_64; /* # of Rx frames in a particular range */ + u64 rx_frames_65_127; + u64 rx_frames_128_255; + u64 rx_frames_256_511; + u64 rx_frames_512_1023; + u64 rx_frames_1024_1518; + u64 rx_frames_1519_max; + + u64 rx_pause; /* # of received pause frames */ + u64 rx_ppp0; /* # of received PPP prio 0 frames */ + u64 rx_ppp1; /* # of received PPP prio 1 frames */ + u64 rx_ppp2; /* # of received PPP prio 2 frames */ + u64 rx_ppp3; /* # of received PPP prio 3 frames */ + u64 rx_ppp4; /* # of received PPP prio 4 frames */ + u64 rx_ppp5; /* # of received PPP prio 5 frames */ + u64 rx_ppp6; /* # of received PPP prio 6 frames */ + u64 rx_ppp7; /* # of received PPP prio 7 frames */ + + u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */ + u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */ + u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */ + u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */ + u64 rx_trunc0; /* buffer-group 0 truncated packets */ + u64 rx_trunc1; /* buffer-group 1 truncated packets */ + u64 rx_trunc2; /* buffer-group 2 truncated packets */ + u64 rx_trunc3; /* buffer-group 3 truncated packets */ +}; + +struct lb_port_stats { + u64 octets; + u64 frames; + u64 bcast_frames; + u64 mcast_frames; + u64 ucast_frames; + u64 error_frames; + + u64 frames_64; + u64 frames_65_127; + u64 frames_128_255; + u64 frames_256_511; + u64 frames_512_1023; + u64 frames_1024_1518; + u64 frames_1519_max; + + u64 drop; + + u64 ovflow0; + u64 ovflow1; + u64 ovflow2; + u64 ovflow3; + u64 trunc0; + u64 trunc1; + u64 trunc2; + u64 trunc3; +}; + +struct tp_tcp_stats { + u32 tcpOutRsts; + u64 tcpInSegs; + u64 tcpOutSegs; + u64 tcpRetransSegs; +}; + +struct tp_usm_stats { + u32 frames; + u32 drops; + u64 octets; +}; + +struct tp_fcoe_stats { + u32 framesDDP; + u32 framesDrop; + u64 octetsDDP; +}; + +struct tp_err_stats { + u32 macInErrs[4]; + u32 hdrInErrs[4]; + u32 tcpInErrs[4]; + u32 tnlCongDrops[4]; + u32 ofldChanDrops[4]; *** DIFF OUTPUT TRUNCATED AT 1000 LINES ***