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Date:      Thu, 10 Oct 2024 14:28:55 +0000
From:      bugzilla-noreply@freebsd.org
To:        fs@FreeBSD.org
Subject:   [Bug 270089] mpr: panic in mpr_complete_command during zpool import
Message-ID:  <bug-270089-3630-AmRAPrDKpn@https.bugs.freebsd.org/bugzilla/>
In-Reply-To: <bug-270089-3630@https.bugs.freebsd.org/bugzilla/>
References:  <bug-270089-3630@https.bugs.freebsd.org/bugzilla/>

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https://bugs.freebsd.org/bugzilla/show_bug.cgi?id=3D270089

--- Comment #21 from Dan Kotowski <dan.kotowski@a9development.com> ---
An interesting update from Solidrun:

https://developer.arm.com/documentation/ddi0517/f/functional-description/co=
nstraints-and-limitations-of-use/axi3-and-axi4-support

> The MMU-500 supports the AXI3 and AXI4 protocols when the sysbardisable_<=
tbuname> input signal is tied HIGH. In such cases, the following AXI3 featu=
res are not supported:
>=20
> Write data interleaving
>=20
> Write data and write address ordering must be the same, otherwise data co=
rruption can occur.

NXP pulls this high in their PBI code. Could write-interleaving enablement =
be a
sysctl?

--=20
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